公开(公告)号：US4514830A

公开(公告)日：1985-04-30

申请号：US344974

申请日：1982-02-02

申请人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

发明人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

IPC分类号： H01L27/112 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C29/789

摘要： An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.

摘要翻译： LSI存储器包括存储器阵列，其包括以矩阵形式布置的常规存储器单元，用于选择连接到存储器阵列的列或行的常用线的常用地址晶体管，用于控制通常地址晶体管的地址线，设置在存储器阵列中的备用存储器单元 存储器阵列，连接到备用存储器单元的备用线路，连接在地址线和备用线路之间的备用地址晶体管，以及连接在备用地址晶体管的源极和地之间的非易失性存储器元件。 通过将非易失性存储器元件中的任何一个置于写入状态，任何一个备用地址晶体管被调节成活动状态，使得备用线可以代替缺陷通常的线。

公开(公告)号：US4668970A

公开(公告)日：1987-05-26

申请号：US803789

申请日：1985-12-02

申请人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Shinichi Minami ,  Toru Kaga

发明人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Shinichi Minami ,  Toru Kaga

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/78 ,  H01L29/7883

摘要： In a semiconductor device which includes an insulation film through which a charge can tunnel, a gate insulation film of a material different from the material of said insulation film or having a thickness different from that of said insulation film, and a floating gate extending over said tunnelable insulation film, the improvement wherein at least two sides of said tunnelable region are bounded by a device separation oxide film.

摘要翻译： 在包括电荷可以隧道穿过的绝缘膜的半导体器件中，与所述绝缘膜的材料不同的或者具有与所述绝缘膜的厚度不同的材料的栅绝缘膜，以及在所述绝缘膜上延伸的浮栅 隧道绝缘膜，其中所述可隧道区域的至少两侧由器件分离氧化物膜限制。

公开(公告)号：US4633438A

公开(公告)日：1986-12-30

申请号：US681027

申请日：1984-12-13

申请人： Hitoshi Kume ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Toru Kaga ,  Yasuo Igura ,  Akihiro Shimizu

发明人： Hitoshi Kume ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Toru Kaga ,  Yasuo Igura ,  Akihiro Shimizu

IPC分类号： G11C11/405 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40

CPC分类号： G11C11/405 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108

摘要： In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.

摘要翻译： 在用于动态操作的3晶体管随机存取存储器中，本发明公开了一种晶体管中的一个堆叠在另一个晶体管上的结构。 用于写入的晶体管设置在用于读取的晶体管上，并且其一个端子与用于判断数据的晶体管的栅电极共同使用。 另一个端子连接到晶体管的一个端子用于读取。 可以获得能够进行极大规模集成的存储单元。

公开(公告)号：US07001818B2

公开(公告)日：2006-02-21

申请号：US10825163

申请日：2004-04-16

申请人： Ryuta Tsuchiya ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Masatada Horiuchi

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  Y10S257/90

摘要： By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

公开(公告)号：US06313012B1

公开(公告)日：2001-11-06

申请号：US09303080

申请日：1999-04-30

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L2130

CPC分类号： H01L27/1203 ,  H01L21/84 ,  Y10S438/977

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US4295265A

公开(公告)日：1981-10-20

申请号：US58501

申请日：1979-07-18

申请人： Masatada Horiuchi ,  Hisao Katto

发明人： Masatada Horiuchi ,  Hisao Katto

IPC分类号： H01L27/112 ,  H01L21/26 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28

CPC分类号： H01L29/1041 ,  H01L21/26 ,  H01L29/7883

摘要： In a nonvolatile semiconductor memory which comprises a source region and a drain region formed on one surface of a semiconductor substrate having one conductivity type, a first insulating film formed on a channel region which is located between the source region and the drain region, a floating gate formed on at least a portion of the first insulating film and which is electrically floated, a control gate formed on the floating gate via a second insulating film, and high impurity concentration regions formed in or near a portion of the channel region and having the same conductivity type as that of the substrate, the floating gate is formed prior to the high impurity concentration regions, and the high impurity concentration regions are formed just outside the channel region by self-alignment with said floating gate using said floating gate as part of a mask.

摘要翻译： 在包括形成在具有一种导电类型的半导体衬底的一个表面上的源区和漏区的非易失性半导体存储器中，形成在位于源区和漏区之间的沟道区上的第一绝缘膜，浮置 形成在第一绝缘膜的至少一部分上并被浮置的栅极，经由第二绝缘膜形成在浮置栅极上的控制栅极和形成在沟道区域的一部分中或附近的高杂质浓度区域，并且具有 与基板相同的导电类型，在高杂质浓度区之前形成浮栅，并且通过使用所述浮栅与所述浮置栅极进行自对准而将高杂质浓度区形成在沟道区的正上方，作为 一个面具

公开(公告)号：US3967310A

公开(公告)日：1976-06-29

申请号：US420590

申请日：1973-11-30

申请人： Masatada Horiuchi ,  Takashi Tokuyama ,  Takao Miyazaki

发明人： Masatada Horiuchi ,  Takashi Tokuyama ,  Takao Miyazaki

IPC分类号： H01L21/00 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/82 ,  H01L23/29 ,  H01L23/532 ,  H01L27/06 ,  H01L29/00 ,  H01L29/51 ,  H01L27/04 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/513 ,  H01L21/00 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/82 ,  H01L23/29 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/0652 ,  H01L29/00 ,  H01L29/51 ,  H01L2924/0002

摘要： After desired impurities are diffused into a semiconductor substrate through a masking layer of SiO.sub.2 formed thereupon so as to form a semiconductor device, the masking layer is completely removed therefrom and thereafter more than two thin layers of different insulating materials are deposited upon the cleaned surface of the semiconductor device thus providing a method of forming a semiconductor device with an improved passivation film thereon. Said insulating materials are selected from the group consisting of silicon dioxide, a silicon nitride, alumina, boro-silicate glass, phospho-silicate glass, alumino-silicate glass, alumino-phospho-silicate glass and alumino-boro-silicate glass, and the thickness of each thin layer is in the range of 300 to 1500 angstroms and the first layer is silicon dioxide.

摘要翻译： 在所需的杂质通过其上形成的SiO 2掩蔽层扩散到半导体衬底中以形成半导体器件之后，完全去除掩模层，然后将不止于两层不同绝缘材料的不同绝缘材料沉积在清洁表面上 因此，半导体器件提供了在其上形成具有改进的钝化膜的半导体器件的方法。 所述绝缘材料选自二氧化硅，氮化硅，氧化铝，硼硅酸盐玻璃，磷硅酸盐玻璃，铝硅酸盐玻璃，铝磷酸硅酸盐玻璃和铝 - 硼硅酸盐玻璃，以及 每个薄层的厚度在300至1500埃的范围内，第一层是二氧化硅。

公开(公告)号：US20060001111A1

公开(公告)日：2006-01-05

申请号：US11155674

申请日：2005-06-20

申请人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/78696 ,  H01L21/28185 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66772

摘要： In a full depletion MISFET, there is a limit to control on a threshold voltage Vth by an impurity concentration in principle when a monocrystalline SOI layer becomes thin on the order of a few tens of nm. It was thus difficult to simultaneously realize predetermined Vth of both n and p types in a complementary MISFET. A gate insulating film for the MISFET is formed as a laminated layer of a metal oxide and an oxynitride. A gate electrode is formed using a polycrystalline Si semiconductor film of the same conductivity type as a source-drain. Predetermined Vth for enhancement are simultaneously achieved by a shift of a flatband voltage produced between the gate insulating film and the gate electrode made of the semiconductor film. Since a variation in Vth due to a statistical fluctuation in the number of impurities with respect to one MISFET can be reduced as compared with the case in which each Vth is controlled by the impurity concentration, Vth and a power supply voltage can both be set low.

摘要翻译： 在完全耗尽的MISFET中，当单晶SOI层变薄到数十nm左右时，在原理上控制阈值电压Vth的限制是有限的。 因此难以在互补的MISFET中同时实现n和p类型的预定Vth。 形成用于MISFET的栅极绝缘膜作为金属氧化物和氧氮化物的叠层。 使用与源极 - 漏极相同的导电类型的多晶硅半导体膜形成栅电极。 用于增强的预定Vth同时通过栅极绝缘膜和由半导体膜制成的栅电极之间产生的平带电压的偏移来实现。 由于相对于一个MISFET而言由于杂质数统计上的波动导致的Vth的变化，与各种Vth被杂质浓度控制的情况相比，可以降低Vth和电源电压两者 。

公开(公告)号：US06690060B2

公开(公告)日：2004-02-10

申请号：US09907714

申请日：2001-07-19

申请人： Masatada Horiuchi ,  Takashi Takahama

发明人： Masatada Horiuchi ,  Takashi Takahama

IPC分类号： H01L29772

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7833

摘要： A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution. As a result, particularly, a miniaturized PMOS with a larger current, punch-through hard and an ultra miniaturized configuration is achieved, and this can be applied also to NMOS, and, therefore, a CMOS with a larger current, punch-through hard and a more miniaturized configuration can be achieved without complicating the fabrication steps, namely, economically.

摘要翻译： 本发明的第一个目的是提供一种绝缘栅场效应晶体管，其实现了栅极电极下面的源极和漏极结区域的结深度和电阻的减小。 另一个目的是提供能够实现大电流和高操作速度的小型化互补型绝缘栅场效应晶体管。 在小型化MOS晶体管中，设置包含In或Ga的低浓度杂质一体化层，使其在高浓度浅源极和漏极扩散层区域的内部具有峰值。 通过这种布置，浅源极和漏极扩散层被杂质集成层吸引，以实现具有高浓度和矩形分布的较浅结。 因此，特别地，实现了具有较大电流，穿透硬度和超小型化配置的小型化PMOS，并且也可以应用于NMOS，因此也可以应用具有较大电流，穿透硬化的CMOS 并且可以实现更小型化的构造，而不会使制造步骤复杂化，即经济地。

公开(公告)号：US5523602A

公开(公告)日：1996-06-04

申请号：US291652

申请日：1994-08-16

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/304 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。