公开(公告)号：US4449063A

公开(公告)日：1984-05-15

申请号：US180452

申请日：1980-08-22

申请人： Hitoshi Ohmichi ,  Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi

发明人： Hitoshi Ohmichi ,  Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi

IPC分类号： H03K19/013 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/084 ,  H03K19/0136 ,  H03K19/088

摘要： A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

摘要翻译： 例如在电子计算机中使用的基本逻辑电路包括输出反相晶体管和开关晶体管，当输出反相器晶体管变化时，输出反相器晶体管的基极 - 发射极结中存储存储在存储电容中的基极电荷 从开启状态到关闭状态。

公开(公告)号：US4388755A

公开(公告)日：1983-06-21

申请号：US207737

申请日：1980-11-17

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi ,  Hitoshi Ohmichi

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi ,  Hitoshi Ohmichi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8222 ,  H01L23/52 ,  H01L27/04 ,  H01L27/082 ,  H01L27/118 ,  H01L29/08

CPC分类号： H01L23/52 ,  H01L27/11801 ,  H01L29/0813 ,  H01L2924/0002

摘要： A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.

摘要翻译： 通过主切片方法制造半导体器件的结构和方法，其中通过利用公共主图和多种不同种类的选择性布线图来制造各种半导体器件。 每个具有多个发射极区域的多个双极晶体管通过采用公共主图案形成在半导体衬底的预定区域或部分中，并且各个双极晶体管的多个发射极区域通过相关布线图案选择性地连接 以形成具有不同的预定DC特性的相应双极晶体管。 当通过主分片方法制造许多不同种类的半导体器件时，通过现有技术将浪费在半导体衬底上的区域大大减少，从而提供增强的面积效率。

公开(公告)号：US4409495A

公开(公告)日：1983-10-11

申请号：US268643

申请日：1981-05-29

申请人： Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

发明人： Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

IPC分类号： H03K3/2893 ,  H03K5/08 ,  H03K3/295

CPC分类号： H03K3/2893

摘要： A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.

摘要翻译： 施密特触发电路具有降低噪声灵敏度和防止振荡的输入电压滞后特性。 在其输入级具有多发射极晶体管，并且在其输出级中具有第二晶体管。 多发射极晶体管包括第一发射极和第二发射极。 响应于施加到多发射极晶体管的基极的输入电压，第一发射极与开关操作相关联。 第二发射极与从第二晶体管的基极通过多发射极晶体管的基极到地的绘制电荷的操作相关联。 使用多发射极晶体管可防止输入电流随着输入电压的下降而大幅度增加。