公开(公告)号：US4449063A

公开(公告)日：1984-05-15

申请号：US180452

申请日：1980-08-22

申请人： Hitoshi Ohmichi ,  Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi

发明人： Hitoshi Ohmichi ,  Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi

IPC分类号： H03K19/013 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/084 ,  H03K19/0136 ,  H03K19/088

摘要： A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

摘要翻译： 例如在电子计算机中使用的基本逻辑电路包括输出反相晶体管和开关晶体管，当输出反相器晶体管变化时，输出反相器晶体管的基极 - 发射极结中存储存储在存储电容中的基极电荷 从开启状态到关闭状态。

公开(公告)号：US4388755A

公开(公告)日：1983-06-21

申请号：US207737

申请日：1980-11-17

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi ,  Hitoshi Ohmichi

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi ,  Hitoshi Ohmichi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8222 ,  H01L23/52 ,  H01L27/04 ,  H01L27/082 ,  H01L27/118 ,  H01L29/08

CPC分类号： H01L23/52 ,  H01L27/11801 ,  H01L29/0813 ,  H01L2924/0002

摘要： A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.

摘要翻译： 通过主切片方法制造半导体器件的结构和方法，其中通过利用公共主图和多种不同种类的选择性布线图来制造各种半导体器件。 每个具有多个发射极区域的多个双极晶体管通过采用公共主图案形成在半导体衬底的预定区域或部分中，并且各个双极晶体管的多个发射极区域通过相关布线图案选择性地连接 以形成具有不同的预定DC特性的相应双极晶体管。 当通过主分片方法制造许多不同种类的半导体器件时，通过现有技术将浪费在半导体衬底上的区域大大减少，从而提供增强的面积效率。

公开(公告)号：US4276556A

公开(公告)日：1981-06-30

申请号：US094436

申请日：1979-11-15

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Hitoshi Ohmichi ,  Yoshiharu Mitono

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Hitoshi Ohmichi ,  Yoshiharu Mitono

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/07 ,  H01L29/73 ,  H01L29/861 ,  H01L29/34

CPC分类号： H01L27/0761 ,  H01L21/761 ,  H01L27/0766

摘要： A semiconductor device including a diode and a bipolar transistor which are connected to each other and formed in an isolated area of a semiconductor layer has a diffused region formed between a base region of the bipolar transistor and a formation region of the diode across the isolated area. The diffused region has the same conductivity type as that of the base region, so that a PNPN diode effect does not occur.

摘要翻译： 包括彼此连接并形成在半导体层的隔离区域中的二极管和双极晶体管的半导体器件具有形成在双极晶体管的基极区域和跨越隔离区域的二极管的形成区域之间的扩散区域 。 扩散区域具有与基极区域相同的导电类型，使得不发生PNPN二极管效应。

公开(公告)号：US5754061A

公开(公告)日：1998-05-19

申请号：US718015

申请日：1996-09-03

申请人： Shinzou Satou ,  Kou Ebihara ,  Akiyoshi Suzuki ,  Keisuke Ishiwata ,  Kouji Miki ,  Hitoshi Ohmichi ,  Tamio Miyamura ,  Masamichi Kamiyama

发明人： Shinzou Satou ,  Kou Ebihara ,  Akiyoshi Suzuki ,  Keisuke Ishiwata ,  Kouji Miki ,  Hitoshi Ohmichi ,  Tamio Miyamura ,  Masamichi Kamiyama

IPC分类号： H03K19/08 ,  H03K19/00 ,  H03K19/003 ,  H03K19/013 ,  H03K19/02 ,  H03K17/04

CPC分类号： H03K19/00353 ,  H03K19/001 ,  H03K19/0136

摘要： A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.

摘要翻译： 一种双CMOS电路包括第一双极型，第二双极晶体管和CMOS控制单元，用于根据施加到输入端的输入信号执行第一和第二双极晶体管的开关控制，并用于控制输出信号经由 输出端基于输入信号。 基于在第一双极晶体管截止时流过所述控制装置的电流，关断单元暂时性将第一双极晶体管的基极连接到低电位侧电源线，使得第一双极晶体管可 快速关闭。