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    Voltage-controlled oscillator and phase-locked loop circuit
    5.
    发明授权
    Voltage-controlled oscillator and phase-locked loop circuit 有权
    压控振荡器和锁相环电路

    公开(公告)号：US08400818B2

    公开(公告)日：2013-03-19

    申请号：US13109157

    申请日：2011-05-17

    申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： G11C7/00

    CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

    摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

    摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

    VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT
    6.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT 有权
    电压控制振荡器和相位锁定环路

    公开(公告)号：US20110310659A1

    公开(公告)日：2011-12-22

    申请号：US13109157

    申请日：2011-05-17

    申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： G11C11/24 ,  H03B5/12 ,  H03B7/06

    CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

    摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

    摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

    MEMORY SYSTEM AND METHOD
    7.
    发明申请
    MEMORY SYSTEM AND METHOD 审中-公开
    记忆系统和方法

    公开(公告)号：US20140019833A1

    公开(公告)日：2014-01-16

    申请号：US14031620

    申请日：2013-09-19

    申请人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    发明人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  H03M13/09

    摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

    摘要翻译： 存储器系统包括存储器控制器和存储器件。 存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组 具有来自存储器控制器的命令/地址通过第三通道。

    Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands
    8.
    发明申请
    Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands 有权
    具有内部命令生成器的集成电路存储器件，其中支持使用独立和相关命令的扩展命令集

    公开(公告)号：US20090097339A1

    公开(公告)日：2009-04-16

    申请号：US12236978

    申请日：2008-09-24

    申请人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

    发明人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18

    摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.

    摘要翻译： 集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。 内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。 例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。 或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。 这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

    Semiconductor memory device and method of controlling the same
    9.
    发明授权
    Semiconductor memory device and method of controlling the same 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08649238B2

    公开(公告)日：2014-02-11

    申请号：US13078218

    申请日：2011-04-01

    申请人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C8/18

    摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.

    摘要翻译： 半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。 存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。 地址控制单元访问存储单元阵列。 逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

    Phase-locked loop and bias generator
    10.
    发明授权
    Phase-locked loop and bias generator 有权
    锁相环和偏置发生器

    公开(公告)号：US08159275B2

    公开(公告)日：2012-04-17

    申请号：US12627730

    申请日：2009-11-30

    申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08

    摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

    摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。