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    Multi-CPU system and computing system having the same
    1.
    发明授权
    Multi-CPU system and computing system having the same 有权
    多CPU系统和计算系统具有相同的功能

    公开(公告)号：US08949534B2

    公开(公告)日：2015-02-03

    申请号：US13741717

    申请日：2013-01-15

    申请人： Hoi Jin Lee ,  Young Min Shin

    发明人： Hoi Jin Lee ,  Young Min Shin

    IPC分类号： G06F12/08 ,  G06F1/32

    CPC分类号： G06F12/0811 ,  G06F1/3234 ,  G06F1/3275 ,  G06F12/0833 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/283 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

    摘要翻译： 一种多CPU数据处理系统，包括：多CPU处理器，包括：第一CPU，配置有至少第一内核，第一高速缓存和配置为访问第一高速缓存的第一高速缓存控制器; 以及配置有至少第二核心的第二CPU和被配置为访问第二高速缓存的第二高速缓存控制器，其中所述第一高速缓存由所述第二高速缓存的共享部分配置。

    High-Speed Multiplexer and Semiconductor Device Including the Same
    2.
    发明申请
    High-Speed Multiplexer and Semiconductor Device Including the Same 有权
    高速多路复用器和包括其的半导体器件

    公开(公告)号：US20100039146A1

    公开(公告)日：2010-02-18

    申请号：US12540465

    申请日：2009-08-13

    申请人： Sung Bae Park ,  Gun Ok Jung ,  Young Min Shin ,  Hoi Jin Lee ,  Chang Jun Choi ,  Min Su Kim

    发明人： Sung Bae Park ,  Gun Ok Jung ,  Young Min Shin ,  Hoi Jin Lee ,  Chang Jun Choi ,  Min Su Kim

    IPC分类号： H03K3/00

    CPC分类号： H03K19/1737 ,  H03K17/005 ,  H03K17/693 ,  H03K19/0013 ,  H03K2217/0036

    摘要： High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.

    摘要翻译： 高速多路复用器包括第一N-1选择电路，其中N是大于1的整数，第二N-1选择电路和输出驱动器。 第一N-1选择电路被配置为响应于第一多位选择信号将所选择的第一输入信号（从N个输入信号中）的真或互补版本路由到其输出，其中N是 大于1的整数。 第二N-1选择电路被配置为响应于第二多位选择信号将所选择的第一输入信号的真实或互补版本路由到其输出。 输出驱动器包括上拉电路，其响应于在第一N-1选择电路的输出处产生的信号，以及下拉电路，其响应于在输出端产生的信号 第二个N到1选择电路。

    High-speed multiplexer and semiconductor device including the same
    3.
    发明授权
    High-speed multiplexer and semiconductor device including the same 有权
    高速多路复用器和包括相同的半导体器件

    公开(公告)号：US07893718B2

    公开(公告)日：2011-02-22

    申请号：US12540465

    申请日：2009-08-13

    申请人： Sung Bae Park ,  Gun Ok Jung ,  Young Min Shin ,  Hoi Jin Lee ,  Chang Jun Choi ,  Min Su Kim

    发明人： Sung Bae Park ,  Gun Ok Jung ,  Young Min Shin ,  Hoi Jin Lee ,  Chang Jun Choi ,  Min Su Kim

    IPC分类号： H03K19/094

    CPC分类号： H03K19/1737 ,  H03K17/005 ,  H03K17/693 ,  H03K19/0013 ,  H03K2217/0036

    摘要： High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.

    摘要翻译： 高速多路复用器包括第一N-1选择电路，其中N是大于1的整数，第二N-1选择电路和输出驱动器。 第一N-1选择电路被配置为响应于第一多位选择信号将所选择的第一输入信号（从N个输入信号中）的真或互补版本路由到其输出，其中N是 大于1的整数。 第二N-1选择电路被配置为响应于第二多位选择信号将所选择的第一输入信号的真实或互补版本路由到其输出。 输出驱动器包括上拉电路，其响应于在第一N-1选择电路的输出处产生的信号，以及下拉电路，其响应于在输出端产生的信号 第二个N到1选择电路。

    Semiconductor IC including pulse generation logic circuit
    4.
    发明授权
    Semiconductor IC including pulse generation logic circuit 有权
    半导体IC包括脉冲生成逻辑电路

    公开(公告)号：US08710891B2

    公开(公告)日：2014-04-29

    申请号：US13613501

    申请日：2012-09-13

    申请人： Hoi Jin Lee

    发明人： Hoi Jin Lee

    IPC分类号： H03K3/00

    CPC分类号： H03K5/135

    摘要： A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.

    摘要翻译： 脉冲发生电路包括以分散布置布置在衬底上并且响应于脉冲信号而工作的存储元件，每个接近存储元件的延迟元件接收时钟信号并提供延迟的输出信号，以及脉冲发生逻辑电路执行 对时钟信号和多个延迟的输出信号进行至少一个逻辑运算以产生脉冲信号。

    PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME
    5.
    发明申请
    PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME 有权
    PSEUDO-STATIC DOMINO LOGIC CIRCUIT和包括其中的设备

    公开(公告)号：US20130246834A1

    公开(公告)日：2013-09-19

    申请号：US13729125

    申请日：2012-12-28

    申请人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    发明人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    IPC分类号： H03K19/096 ,  G06F1/08

    CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0963

    摘要： A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

    摘要翻译： 多米诺逻辑电路包括在锁存器和触发器之间串联连接的多个多米诺逻辑级和产生具有第一占空比的时钟信号的时钟信号发生器和具有第二占空比的触发器时钟信号。 锁存器和多米诺逻辑级分别响应于从第一时钟信号导出的多米诺骨牌时钟信号而工作。 触发器响应于触发器时钟信号而工作。

    FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS
    6.
    发明申请
    FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS 有权
    无袖NP逻辑逻辑电路及相关设备

    公开(公告)号：US20130246819A1

    公开(公告)日：2013-09-19

    申请号：US13795852

    申请日：2013-03-12

    申请人： Ken Keon Shin ,  Hoi Jin Lee ,  Gun Ok Jung ,  Min Su Kim

    发明人： Ken Keon Shin ,  Hoi Jin Lee ,  Gun Ok Jung ,  Min Su Kim

    IPC分类号： G06F1/32 ,  G06F1/04 ,  H03K19/00

    CPC分类号： G06F1/32 ,  G06F1/04 ,  H03K19/0008 ,  H03K19/0963

    摘要： A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.

    摘要翻译： 多米诺骨牌逻辑电路包括响应于时钟信号对第一动态节点预充电的预充电电路，第一逻辑网络响应于第一数据信号确定第一动态节点的逻辑电平，反相器接收时钟信号 响应于逆变器的输出信号而放电第二动态节点的放电电路，以及响应于至少一个第二数据信号和第一动态节点的输出信号确定第二动态节点的逻辑电平的第二逻辑网络 节点。

    Pseudo-static domino logic circuit and apparatuses including same
    7.
    发明授权
    Pseudo-static domino logic circuit and apparatuses including same 有权
    伪静态多米诺逻辑电路及包括其的设备

    公开(公告)号：US08810279B2

    公开(公告)日：2014-08-19

    申请号：US13729125

    申请日：2012-12-28

    申请人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    发明人： Ken Keon Shim ,  Hoi Jin Lee ,  Gun Ok Jung

    IPC分类号： H03K19/00

    CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0963

    摘要： A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

    摘要翻译： 多米诺逻辑电路包括串联连接在锁存器和触发器之间的多个多米诺逻辑级和产生具有第一占空比的时钟信号的时钟信号发生器和具有第二占空比的触发器时钟信号。 锁存器和多米诺逻辑级分别响应于从第一时钟信号导出的多米诺骨牌时钟信号而工作。 触发器响应于触发器时钟信号而工作。

    Integrated circuit for compression mode scan test
    8.
    发明授权
    Integrated circuit for compression mode scan test 有权
    用于压缩模式扫描测试的集成电路

    公开(公告)号：US08539293B2

    公开(公告)日：2013-09-17

    申请号：US13098749

    申请日：2011-05-02

    申请人： Heon-Hee Lee ,  Hoi Jin Lee

    发明人： Heon-Hee Lee ,  Hoi Jin Lee

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318547

    摘要： An integrated circuit for performing a design for testability (DFT) scan test is provided. The integrated circuit includes at least one scan chain including a plurality of flip-flops, at least one interface scan chain including a plurality of flip-flops, a decompressor configured to be connected with an input terminal of the at least one interface scan chain and to decompress a first input signal and then transmit it to the at least one scan chain, a compressor configured to be connected with an output terminal of the at least one scan chain and to compress an output signal of the at least one scan chain, and at least one multiplexer configured to be connected with the decompressor and to selectively output an output signal of the decompressor or a second input signal in response to a control signal.

    摘要翻译： 提供了用于执行可测性（DFT）扫描测试设计的集成电路。 所述集成电路包括至少一个包括多个触发器的扫描链，包括多个触发器的至少一个接口扫描链，被配置为与所述至少一个接口扫描链的输入端连接的解压缩器，以及 解压缩第一输入信号，然后将其发送到所述至少一个扫描链，所述压缩器被配置为与所述至少一个扫描链的输出端连接并且压缩所述至少一个扫描链的输出信号，以及 至少一个多路复用器，被配置为与解压缩器连接，并且响应于控制信号选择性地输出解压缩器的输出信号或第二输入信号。

    SYSTEM ON CHIP (SOC), METHOD OF OPERATING THE SOC, AND SYSTEM HAVING THE SOC
    9.
    发明申请
    SYSTEM ON CHIP (SOC), METHOD OF OPERATING THE SOC, AND SYSTEM HAVING THE SOC 审中-公开
    系统芯片（SOC），操作SOC的方法和具有SOC的系统

    公开(公告)号：US20130305078A1

    公开(公告)日：2013-11-14

    申请号：US13734176

    申请日：2013-01-04

    申请人： Heon-Hee Lee ,  Hoi Jin Lee ,  Jeong Lae Cho

    发明人： Heon-Hee Lee ,  Hoi Jin Lee ,  Jeong Lae Cho

    IPC分类号： G06F1/08

    CPC分类号： G06F1/08

    摘要： A data processing system, comprising: a PLL configured to receive a reference clock and to generate a common clock; a processing unit configured to output an operation condition data based on one of temperature, voltage, or process information; and at least two data processing circuits, each comprising: a first clock signal generator configured to receive the common clock signal, the first clock signal generator having a first clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data; and a second clock signal generator configured to receive the common clock signal, the second clock signal generator having a second clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data.

    摘要翻译： 一种数据处理系统，包括：被配置为接收参考时钟并产生公共时钟的PLL; 处理单元，被配置为基于温度，电压或处理信息之一输出操作条件数据; 以及至少两个数据处理电路，每个数据处理电路包括：第一时钟信号发生器，被配置为接收所述公共时钟信号，所述第一时钟信号发生器具有第一时钟延迟调整电路，其被配置为基于所述操作条件数据来调整时钟信号传播延迟; 以及第二时钟信号发生器，被配置为接收所述公共时钟信号，所述第二时钟信号发生器具有被配置为基于所述操作条件数据来调整时钟信号传播延迟的第二时钟延迟调整电路。