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公开(公告)号：US07051193B2
公开(公告)日：2006-05-23
申请号：US09819339
申请日：2001-03-28
申请人： Hong Wang , Christopher J. Hughes , Ralph Kling , Yong-Fong Lee , Daniel M. Lavery , John Shen , Jamison Collins
发明人： Hong Wang , Christopher J. Hughes , Ralph Kling , Yong-Fong Lee , Daniel M. Lavery , John Shen , Jamison Collins
IPC分类号： G06F9/38
CPC分类号： G06F9/325 , G06F9/30072 , G06F9/30101 , G06F9/384 , G06F9/3842
摘要： Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.
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公开(公告)号：US20050223199A1
公开(公告)日：2005-10-06
申请号：US10816103
申请日：2004-03-31
申请人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译： 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。
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公开(公告)号：US20080163366A1
公开(公告)日：2008-07-03
申请号：US11648009
申请日：2006-12-29
申请人： Gautham Chinya , Perry Wang , Hong Wang , Jamison Collins , Richard A. Hankins , Per Hammarlund , John Shen
发明人： Gautham Chinya , Perry Wang , Hong Wang , Jamison Collins , Richard A. Hankins , Per Hammarlund , John Shen
IPC分类号： H04L9/32
CPC分类号： G06F9/468 , G06F12/1027 , G06F2212/1052
摘要： In one embodiment, the present invention includes a method for receiving a request from a user-level agent for programming of a user-level privilege for at least one architectural resource of an application-managed sequencer (AMS) and programming the user-level privilege for the at least one architectural resource using an operating system-managed sequencer (OMS) coupled to the AMS. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于从用户级代理接收针对应用管理的定序器（AMS）的至少一个架构资源的用户级特权的编程并且编程用户级特权的请求的方法 对于使用耦合到AMS的操作系统管理的定序器（OMS）的至少一个架构资源。 描述和要求保护其他实施例。
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4.发明申请Mechanism to exploit synchronization overhead to improve multithreaded performance 有权利用同步开销来提高多线程性能的机制公开(公告)号：US20050149697A1
公开(公告)日：2005-07-07
申请号：US11070991
申请日：2005-03-02
申请人： Natalie Enright , Jamison Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
发明人： Natalie Enright , Jamison Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/4843 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchronization object. The event detector can cause a first thread switch in response to the long latency event associated with the synchronization object. The apparatus may also include a spin detector to detect that the synchronization object is a contended synchronization object. The spin detector can cause a second thread switch in response to the detection of the contended synchronization object to enable a spin detect response.
摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。 在一个实施例中，装置包括执行多个指令的执行资源和用于检测与同步对象相关联的长延迟事件的事件检测器。 事件检测器可以响应于与同步对象相关联的长等待时间事件而导致第一线程切换。 该装置还可以包括检测同步对象是竞争同步对象的自旋检测器。 响应于竞争的同步对象的检测，自旋检测器可以引起第二线程切换以启用自旋检测响应。
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公开(公告)号：US08074274B2
公开(公告)日：2011-12-06
申请号：US11648009
申请日：2006-12-29
申请人： Hong Wang , Gautham Chinya , Perry Wang , Jamison Collins , Richard A. Hankins , Per Hammarlund , John Shen
发明人： Hong Wang , Gautham Chinya , Perry Wang , Jamison Collins , Richard A. Hankins , Per Hammarlund , John Shen
IPC分类号： G06F7/00
CPC分类号： G06F9/468 , G06F12/1027 , G06F2212/1052
摘要： In one embodiment, the present invention includes a method for receiving a request from a user-level agent for programming of a user-level privilege for at least one architectural resource of an application-managed sequencer (AMS) and programming the user-level privilege for the at least one architectural resource using an operating system-managed sequencer (OMS) coupled to the AMS. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于从用户级代理接收针对应用管理的定序器（AMS）的至少一个架构资源的用户级特权的编程并且编程用户级特权的请求的方法 对于使用耦合到AMS的操作系统管理的定序器（OMS）的至少一个架构资源。 描述和要求保护其他实施例。
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公开(公告)号：US20090077348A1
公开(公告)日：2009-03-19
申请号：US11901178
申请日：2007-09-14
申请人： Perry Wang , Jamison Collins , Hong Wang
发明人： Perry Wang , Jamison Collins , Hong Wang
CPC分类号： G06F9/30 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F15/17368 , G06F15/7832
摘要： In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer via a dedicated interconnect, detecting the assertion signal in the accelerators and communicating a request for a lock on a second interconnect coupled to the first instruction sequencer and the accelerators, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer via the second interconnect. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将断言信号从第一指令定序器传送到经由专用互连耦合到第一指令定序器的多个加速器的方法，检测加速器中的断言信号并传送锁定请求 在耦合到所述第一指令定序器和所述加速器的第二互连上，以及通过经由所述第二互连将所述加速器的用于所述加速器的注册消息通信到所述第一指令定序器来登记实现所述锁定的加速器。 描述和要求保护其他实施例。
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7.发明申请公开(公告)号：US20080256330A1
公开(公告)日：2008-10-16
申请号：US11786920
申请日：2007-04-13
申请人： Perry Wang , Jamison Collins , Gautham Chinya , Hong Jiang , Hong Wang , Xinmin Tian , Guei-Yuan Lueh
发明人： Perry Wang , Jamison Collins , Gautham Chinya , Hong Jiang , Hong Wang , Xinmin Tian , Guei-Yuan Lueh
IPC分类号： G06F15/00
CPC分类号： G06F9/3879 , G06F8/447 , G06F8/45 , G06F8/47 , G06F9/3851
摘要： Compiling a source code program for a heterogeneous multi-core processor having a first instruction sequencer, having a first instruction set architecture, an accelerator to the first instruction sequencer, wherein the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer having a second instruction set architecture, the source code program having specified therein a region of source code for the first instruction set architecture of the processor and a region of source code for the second instruction set architecture of the processor.
摘要翻译： 编译具有第一指令定序器的异构多核处理器的源代码程序，第一指令定序器具有第一指令集架构，加速器到第一指令定序器，其中加速器包括关于第一指令定序器的异质资源， 指令集架构，源代码程序在其中指定了用于处理器的第一指令集架构的源代码区域和处理器的第二指令集架构的源代码区域。
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8.发明授权Apparatus and method for enabling inter-sequencer communication following lock competition and accelerator registration 有权用于启用锁定竞争和加速器登记之后的序列发生器通信的装置和方法公开(公告)号：US08380963B2
公开(公告)日：2013-02-19
申请号：US13017225
申请日：2011-01-31
申请人： Perry Wang , Jamison Collins , Hong Wang
发明人： Perry Wang , Jamison Collins , Hong Wang
IPC分类号： G06F13/00
CPC分类号： G06F9/30 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F15/17368 , G06F15/7832
摘要： In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将断言信号从第一指令定序器传送到耦合到第一指令定序器的多个加速器，检测加速器中的断言信号并传送锁定请求的方法， 加速器，其通过将加速器的注册消息通信给第一指令定序器来实现锁定。 描述和要求保护其他实施例。
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9.发明申请Providing A Dedicated Communication Path Separate From A Second Path To Enable Communication Between Compliant Sequencers Using An Assertion Signal 有权提供专用通信路径与第二条路径分离，以使用断言信号实现顺序排序器之间的通信公开(公告)号：US20110125985A1
公开(公告)日：2011-05-26
申请号：US13017225
申请日：2011-01-31
申请人： Perry Wang , Jamison Collins , Hong Wang
发明人： Perry Wang , Jamison Collins , Hong Wang
CPC分类号： G06F9/30 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F15/17368 , G06F15/7832
摘要： In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将断言信号从第一指令定序器传送到耦合到第一指令定序器的多个加速器，检测加速器中的断言信号并传送锁定请求的方法， 加速器，其通过将加速器的注册消息通信给第一指令定序器来实现锁定。 描述和要求保护其他实施例。
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10.发明申请Providing A Dedicated Communication Path Separate From A Second Path To Enable Communication Between Complaint Sequencers Of A Processor Using An Assertion Signal 有权提供从第二条路径分离的专用通信路径，以实现使用断言信号的处理器的投诉排序器之间的通信公开(公告)号：US20130080746A1
公开(公告)日：2013-03-28
申请号：US13682111
申请日：2012-11-20
申请人： Perry Wang , Jamison Collins , Hong Wang
发明人： Perry Wang , Jamison Collins , Hong Wang
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F15/17368 , G06F15/7832
摘要： In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将断言信号从第一指令定序器传送到耦合到第一指令定序器的多个加速器，检测加速器中的断言信号并传送锁定请求的方法， 加速器，其通过将加速器的注册消息通信给第一指令定序器来实现锁定。 描述和要求保护其他实施例。
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