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1.发明授权Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution 有权方法和系统提供并发用户级，非特权共享资源线程的创建和执行公开(公告)号：US09189230B2
公开(公告)日：2015-11-17
申请号：US10816103
申请日：2004-03-31
申请人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译： 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。
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2.发明授权公开(公告)号：US08661206B2
公开(公告)日：2014-02-25
申请号：US12943848
申请日：2010-11-10
IPC分类号： G06F13/00
CPC分类号： G06F12/0806 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3857 , G06F9/3859 , G06F9/467 , G06F9/528 , G06F12/0831 , G06F12/084 , G06F12/0848 , G06F2212/60 , G06F2212/621
摘要： Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.
摘要翻译： 本发明的实施例涉及计算机系统中事务性存储器访问的混合硬件和软件实现。 包括事务高速缓存和常规高速缓存的处理器在包括策略管理器的计算机系统中被利用，该策略管理器选择第一模式（硬件模式）或第二模式（软件模式）之一来实现事务存储器访问。 在硬件模式中，事务缓存用于执行读写存储器操作，并且在软件模式中，常规高速缓存用于执行读写存储器操作。
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公开(公告)号：US08578097B2
公开(公告)日：2013-11-05
申请号：US13280117
申请日：2011-10-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0862 , G06F12/0877 , G06F12/0891 , G06F12/0897 , G06F2212/6026 , G06F2212/62 , G11C7/1072 , G11C7/1075 , Y02D10/13
摘要： A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
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4.发明申请Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems 有权在多处理器系统上分散收集非结构化流数据的智能内存架构公开(公告)号：US20120042121A1
公开(公告)日：2012-02-16
申请号：US13280117
申请日：2011-10-24
CPC分类号： G06F12/0806 , G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0862 , G06F12/0877 , G06F12/0891 , G06F12/0897 , G06F2212/6026 , G06F2212/62 , G11C7/1072 , G11C7/1075 , Y02D10/13
摘要： A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
摘要翻译： 分散/收集技术优化非结构化流式存储器访问，通过仅访问精细粒度的有用数据来提供片外带宽效率，并通过支持地址计算，数据混洗和格式转换来卸载内存访问开销。
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5.发明申请Method and apparatus for register stack implementation using micro-operations 审中-公开使用微操作的寄存器堆栈实现的方法和装置公开(公告)号：US20050102494A1
公开(公告)日：2005-05-12
申请号：US10712618
申请日：2003-11-12
申请人： Edward Grochowski , Jeffrey Rupley , Partha Kundu
发明人： Edward Grochowski , Jeffrey Rupley , Partha Kundu
CPC分类号： G06F9/3017
摘要： Disclosed are embodiments of an apparatus, system, and method for implementing a register stack using micro-operations. A register stack engine generates a plurality of micro-operations to implement a memory operation in support of register windowing, such as spill or fill to/from a backing store. These micro-operations are inserted into an execution pipeline along with other micro-operations not related to register stack operation.
摘要翻译： 公开了用于使用微操作来实现寄存器堆栈的装置，系统和方法的实施例。 寄存器堆栈引擎产生多个微操作以实现支持寄存器窗口的存储器操作，诸如从后备存储器溢出或填充到后备存储器。 这些微操作与其他与寄存器堆栈操作无关的微操作被插入到执行流水线中。
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6.发明申请公开(公告)号：US20170039068A1
公开(公告)日：2017-02-09
申请号：US15299452
申请日：2016-10-20
IPC分类号： G06F9/30 , G06F9/46 , G06F12/084
CPC分类号： G06F12/0806 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3857 , G06F9/3859 , G06F9/467 , G06F9/528 , G06F12/0831 , G06F12/084 , G06F12/0848 , G06F2212/60 , G06F2212/621
摘要： Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.
摘要翻译： 本发明的实施例涉及计算机系统中事务性存储器访问的混合硬件和软件实现。 包括事务高速缓存和常规高速缓存的处理器在包括策略管理器的计算机系统中被利用，该策略管理器选择第一模式（硬件模式）或第二模式（软件模式）之一来实现事务存储器访问。 在硬件模式中，事务缓存用于执行读写存储器操作，并且在软件模式中，常规高速缓存用于执行读写存储器操作。
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7.发明申请SCATTER-GATHER INTELLIGENT MEMORY ARCHITECTURE FOR UNSTRUCTURED STREAMING DATA ON MULTIPROCESSOR SYSTEMS 有权用于多处理器系统上不间断流动数据的分布式智能存储器架构公开(公告)号：US20140040542A1
公开(公告)日：2014-02-06
申请号：US14048291
申请日：2013-10-08
CPC分类号： G06F12/0806 , G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0862 , G06F12/0877 , G06F12/0891 , G06F12/0897 , G06F2212/6026 , G06F2212/62 , G11C7/1072 , G11C7/1075 , Y02D10/13
摘要： A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
摘要翻译： 分散/收集技术优化非结构化流式存储器访问，通过仅访问精细粒度的有用数据来提供片外带宽效率，并通过支持地址计算，数据混洗和格式转换来卸载内存访问开销。
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8.发明授权公开(公告)号：US07856537B2
公开(公告)日：2010-12-21
申请号：US10956179
申请日：2004-09-30
CPC分类号： G06F12/0806 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3857 , G06F9/3859 , G06F9/467 , G06F9/528 , G06F12/0831 , G06F12/084 , G06F12/0848 , G06F2212/60 , G06F2212/621
摘要： Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.
摘要翻译： 本发明的实施例涉及计算机系统中事务性存储器访问的混合硬件和软件实现。 包括事务高速缓存和常规高速缓存的处理器在包括策略管理器的计算机系统中被利用，该策略管理器选择第一模式（硬件模式）或第二模式（软件模式）之一来实现事务存储器访问。 在硬件模式中，事务缓存用于执行读写存储器操作，并且在软件模式中，常规高速缓存用于执行读写存储器操作。
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公开(公告)号：US20080112432A1
公开(公告)日：2008-05-15
申请号：US11559793
申请日：2006-11-14
申请人： Amit Kumar , Partha Kundu
发明人： Amit Kumar , Partha Kundu
IPC分类号： H04J3/02
CPC分类号： H04L49/15 , H04L45/00 , H04L45/06 , H04L49/253
摘要： A technique to route data according to a speculative priority. At least one embodiment detects a conflict among a number of data received by the router, assigns a speculative priority to one of the data in a first clock portion and sends the speculatively prioritized data to a receiving agent in a subsequent clock portion.
摘要翻译： 根据推测优先级路由数据的技术。 至少一个实施例检测由路由器接收的数量的数据之间的冲突，将推测优先级分配给第一时钟部分中的数据之一，并将推测性优先级数据发送到后续时钟部分中的接收代理。
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公开(公告)号：US20050223199A1
公开(公告)日：2005-10-06
申请号：US10816103
申请日：2004-03-31
申请人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译： 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。
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