Method and apparatus for efficient utilization for prescient instruction prefetch
    8.
    发明申请
    Method and apparatus for efficient utilization for prescient instruction prefetch 有权
    有效利用预编程指令预取的方法和装置

    公开(公告)号:US20050055541A1

    公开(公告)日:2005-03-10

    申请号:US10658072

    申请日:2003-09-08

    IPC分类号: G06F9/30 G06F9/38

    摘要: Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.

    摘要翻译: 装置,系统和方法的实施例通过一个或多个推测性线程增强在指令预取期间处理器资源利用的效率。 利用重命名逻辑和映射表来对推测性线程指令流中的指令进行滤波。 映射表包括一个肯定事件位,用于指示相关联的物理寄存器的内容是否反映由主线程计算的值。 线程进度信标表用于跟踪主线程和推测式辅助线程的相对进度。 基于线程进度信标表中的信息,主线程可能会影响不太可能为主线程提供性能优势的辅助线程的终止。