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    High performance shared cache
    1.
    发明授权
    High performance shared cache 失效
    高性能共享缓存

    公开(公告)号：US06101589A

    公开(公告)日：2000-08-08

    申请号：US58431

    申请日：1998-04-10

    申请人： Horst Fuhrmann ,  Jorg Wedeck ,  Dieter Wendel ,  Udo Wille

    发明人： Horst Fuhrmann ,  Jorg Wedeck ,  Dieter Wendel ,  Udo Wille

    IPC分类号： G06F12/084 ,  G06F12/0855 ,  G06F12/00

    CPC分类号： G06F12/084 ,  G06F12/0857

    摘要： A high performance cache unit in a multiprocessing computer system comprises a shared level n cache 15 which is divided into a number of independently operated cache cores each of which containing a cache array for being used as buffer between plurality of processing units PU0-PU1 and a memory 18. Data requests and response requests issued by the processing units are separately executed in an interleaved mode to achieve a high degree of concurrency. For this purpose each cache core comprises arbitration circuits 101, 106 for an independent selection of pending data requests and response requests for execution. Selected data requests are identified by a cache directory lookup as linefetch-match or linefetch-miss operations and separately stored during their execution in operation registers 112, 114. Selected response requests are stored independently of the data requests in registers 105, 108, 109 and successively executed during free operation cycles which are not used by the execution of data requests. In this manner each of the cache cores can concurrently perform a linefetch-match operation, a linefetch-miss operation and a store operation for one processing unit or for a number of processing units.

    摘要翻译： 多处理计算机系统中的高性能高速缓存单元包括共享级n高速缓存15，其被分成多个独立操作的高速缓存核心，每个高速缓存核心包含用于在多个处理单元PU0-PU1和 存储器18.处理单元发出的数据请求和响应请求以交错模式分开执行以实现高度的并发性。 为此，每个缓存核心包括仲裁电路101,106，用于独立选择待处理的数据请求和执行的响应请求。 所选择的数据请求由高速缓存目录查找标识为线取样匹配或线取出错误操作，并且在其执行期间在操作寄存器112,114中单独存储。所选择的响应请求被独立于数据请求存储在寄存器105,108,109和 在执行数据请求时不使用的自由运行循环中连续执行。 以这种方式，每个高速缓存核心可以同时对一个处理单元或多个处理单元执行线取出匹配操作，线取出缺失操作和存储操作。

    Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure
    3.
    发明授权
    Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure 失效
    逻辑总线结构包括具有多级缓存存储器结构的多处理器系统的多个物理总线

    公开(公告)号：US5889969A

    公开(公告)日：1999-03-30

    申请号：US737951

    申请日：1996-11-27

    申请人： Klaus Jorg Getzlaff ,  Bernd Leppla ,  Hans-Warner Tast ,  Udo Wille

    发明人： Klaus Jorg Getzlaff ,  Bernd Leppla ,  Hans-Warner Tast ,  Udo Wille

    IPC分类号： G06F3/00 ,  G06F12/08 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F15/16 ,  G06F15/167 ,  G06F13/00

    CPC分类号： G06F13/4022 ,  G06F13/1657

    摘要： An improved multiple bus system for a multiprocessor computer system is disclosed for a computer system having a multiple level cache memory structure. The system includes one or more logical busses each including two or more physical busses for coupling multiple processors to a memory unit. Each logical bus is coupled to a bus switching unit which in turn couples all of the processors in the multiprocessor system to a memory unit over the physical busses comprising the logical bus. The system further manages near end signal reception problems caused by multiple processors electrically interconnected over such a bus system.

    摘要翻译： PCT No.PCT / EP95 / 01140 Sec。 371日期：1996年11月27日 102（e）日期1996年11月27日PCT 1995年3月27日PCT公布。 公开号WO96 / 30842 日期1996年10月3日公开了一种用于具有多级高速缓冲存储器结构的计算机系统的用于多处理器计算机系统的改进的多总线系统。 该系统包括一个或多个逻辑总线，每个逻辑总线包括用于将多个处理器耦合到存储器单元的两个或多个物理总线。 每个逻辑总线耦合到总线切换单元，总线切换单元又将多处理器系统中的所有处理器通过包括逻辑总线的物理总线耦合到存储器单元。 该系统进一步管理由这种总线系统电互连的多个处理器引起的近端信号接收问题。

    Memory card interface method using multiplexed storage protect key to indicate command acceptance
    4.
    发明授权
    Memory card interface method using multiplexed storage protect key to indicate command acceptance 失效
    存储卡接口方式采用多路存储保护密钥来表示命令接受

    公开(公告)号：US06182174B2

    公开(公告)日：2001-01-30

    申请号：US09059221

    申请日：1998-04-13

    申请人： Kevin W. Kark ,  William Wu Shen ,  Russell W. Lavallee ,  Udo Wille ,  Hartmut Ulland ,  Walter Lipponer

    发明人： Kevin W. Kark ,  William Wu Shen ,  Russell W. Lavallee ,  Udo Wille ,  Hartmut Ulland ,  Walter Lipponer

    IPC分类号： G06F1342

    CPC分类号： G06F12/1466

    摘要： A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.

    摘要翻译： S / 390系统的存储控制器和存储卡之间的存储器接口使用S / 390存储保护（SP）密钥作为存储卡接受存储命令的指示或协议。 当返回SP密钥时，该命令被认为被存储卡接受，密钥将被处理器用于根据S / 390架构的存储验证。 在存储卡检测到与命令相关的错误的情况下，它将通过存储器状态总线返回错误响应代码。 存储器状态总线被复用以服务现有的架构要求以及存储器控制器和存储卡之间握手的指示器。

    Method for executing branch instructions by processing loop end conditions in a second processor
    6.
    发明授权
    Method for executing branch instructions by processing loop end conditions in a second processor 失效
    用于通过处理第二处理器中的循环结束条件来执行分支指令的方法

    公开(公告)号：US5634047A

    公开(公告)日：1997-05-27

    申请号：US699074

    申请日：1996-06-10

    申请人： Klaus J. Getzlaff ,  Udo Wille ,  Brigitte Roethe ,  Wilhelm Haller ,  Hans-Werner Tast

    发明人： Klaus J. Getzlaff ,  Udo Wille ,  Brigitte Roethe ,  Wilhelm Haller ,  Hans-Werner Tast

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F9/325

    摘要： A method and system for executing branch or other instructions in a loop. A loop end condition is evaluated in a fixed point unit while floating point instructions are evaluated in a floating point unit. In a first execution of the instructions in the loop, the loop end condition is processed as in prior art. A branch target instruction is stored in a branch target register and an instruction address of the branch target instruction is stored in a branch address register. However, on subsequent execution of the instructions in the loop, the branch condition is evaluated and, if it is fulfilled, once the end of the loop is detected by comparison of the effective address of the next instruction to be executed with the contents of the branch address register, the effective address of the first instruction in the loop is passed from the branch target register to an operations register.

    摘要翻译： 用于在循环中执行分支或其他指令的方法和系统。 循环结束条件在固定点单元中进行评估，而浮点指令在浮点单元中进行求值。 在循环中的指令的第一次执行中，循环结束条件如现有技术那样被处理。 分支目标指令存储在分支目标寄存器中，分支目标指令的指令地址存储在分支地址寄存器中。 然而，在循环中的指令的随后执行中，评估分支条件，并且如果满足，一旦通过将要执行的下一个指令的有效地址与 分支地址寄存器，循环中的第一条指令的有效地址从分支目标寄存器传递到操作寄存器。