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1.发明授权Method for executing branch instructions by processing loop end conditions in a second processor 失效用于通过处理第二处理器中的循环结束条件来执行分支指令的方法
公开(公告)号：US5634047A
公开(公告)日：1997-05-27
申请号：US699074
申请日：1996-06-10
CPC分类号： G06F9/3804 , G06F9/30058 , G06F9/325
摘要： A method and system for executing branch or other instructions in a loop. A loop end condition is evaluated in a fixed point unit while floating point instructions are evaluated in a floating point unit. In a first execution of the instructions in the loop, the loop end condition is processed as in prior art. A branch target instruction is stored in a branch target register and an instruction address of the branch target instruction is stored in a branch address register. However, on subsequent execution of the instructions in the loop, the branch condition is evaluated and, if it is fulfilled, once the end of the loop is detected by comparison of the effective address of the next instruction to be executed with the contents of the branch address register, the effective address of the first instruction in the loop is passed from the branch target register to an operations register.
摘要翻译： 用于在循环中执行分支或其他指令的方法和系统。 循环结束条件在固定点单元中进行评估，而浮点指令在浮点单元中进行求值。 在循环中的指令的第一次执行中，循环结束条件如现有技术那样被处理。 分支目标指令存储在分支目标寄存器中，分支目标指令的指令地址存储在分支地址寄存器中。 然而，在循环中的指令的随后执行中，评估分支条件，并且如果满足，一旦通过将要执行的下一个指令的有效地址与 分支地址寄存器，循环中的第一条指令的有效地址从分支目标寄存器传递到操作寄存器。
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公开(公告)号：US5311519A
公开(公告)日：1994-05-10
申请号：US871160
申请日：1992-04-20
摘要： A multiplexer circuit which is built up from a series of smaller submultiplexers (241-247, 251-254). It selects a number of adjacent bits, bytes or words from one register and places them in the same order in a second register. The multiplexer can be used in cache memories or instruction buffers.
摘要翻译： 多路复用器电路，由一系列较小的子多路复用器（241-247,251-254）构成。 它从一个寄存器中选择一些相邻的位，字节或字，并将它们以相同的顺序放置在第二个寄存器中。 多路复用器可用于高速缓冲存储器或指令缓冲器。
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公开(公告)号：US08751749B2
公开(公告)日：2014-06-10
申请号：US13159590
申请日：2011-06-14
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
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公开(公告)号：US20130339615A1
公开(公告)日：2013-12-19
申请号：US13524386
申请日：2012-06-15
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
摘要翻译： 实施例涉及控制事务和非交易存储的可观察性。 一方面包括接收一个或多个存储指令。 一个或多个存储指令在活动事务中启动并且包括存储数据。 活动事务有效地延迟将存储提交到存储器，直到成功完成活动事务。 存储数据存储在本地存储缓冲器中，导致本地存储缓冲器从第一状态到第二状态的改变。 接收到有效事务终止的信号。 如果活动事务已经异常终止，则：如果存储数据由事务存储指令存储，则本地存储缓冲区被恢复到第一状态，并且如果存储指令是非事务性的则将其传播到共享高速缓存。
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5.发明申请METHOD TO VERIFY AN IMPLEMENTED COHERENCY ALGORITHM OF A MULTI PROCESSOR ENVIRONMENT 失效验证多处理器环境的实现的相似算法的方法公开(公告)号：US20100146210A1
公开(公告)日：2010-06-10
申请号：US12328242
申请日：2008-12-04
CPC分类号： G06F12/0815
摘要： A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of: generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events, wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further a single processor model and a computer program product to execute said method are described.
摘要翻译： 描述了在单个处理器模型上验证多处理器环境的实现的一致性算法的方法，包括以下步骤：生成反映多处理器环境内的单个处理器的专用高速缓存层级的参考模型，以刺激专用高速缓存层级 具有来自核心侧和/或来自嵌套侧的模拟请求和/或交叉无效，基于接口事件设置两个构建日期和两个到期日期，扩充专用高速缓存层级中可用的所有数据，其中多处理器一致性不是 观察缓存层次结构是否已将数据返回给处理器，其过期日期早于之前使用的所有数据的最新构建日期。 此外，描述了执行所述方法的单个处理器模型和计算机程序产品。
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公开(公告)号：US20100030968A1
公开(公告)日：2010-02-04
申请号：US12184165
申请日：2008-07-31
申请人： Eberhard Pasch , Hans-Werner Tast , Achim Haessler , Markus Nosse , Elmar Zipp
发明人： Eberhard Pasch , Hans-Werner Tast , Achim Haessler , Markus Nosse , Elmar Zipp
IPC分类号： G06F12/08
CPC分类号： G06F12/0261 , G06F12/0802
摘要： A computer implemented method of cache bounded reference counting for computer languages having automated memory management in which, for example, a reference to an object “Z” initially stored in an object “O” is fetched and the cache hardware is queried whether the reference to the object “Z” is a valid reference, is in the cache, and has a continuity flag set to “on”. If so, the object “O” is locked for an update, a reference counter is decremented for the object “Z” if the object “Z” resides in the cache, and a return code is set to zero to indicate that the object “Z” is de-referenced and that its storage memory can be released and re-used if the reference counter for the object “Z” reaches zero. Thereafter, the cache hardware is similarly queried regarding an object “N” that will become a new reference of object “O”.
摘要翻译： 具有自动存储器管理的计算机语言的高速缓存有界引用计数的计算机实现方法，其中例如对最初存储在对象“O”中的对象“Z”的引用被查询，并且查询高速缓存硬件是否被引用 对象“Z”是有效的引用，位于缓存中，并具有设置为“开”的连续性标志。 如果是这样，对象“O”被锁定以进行更新，如果对象“Z”驻留在高速缓存中，对象“Z”的引用计数器递减，并且将返回码设置为零以指示对象“ Z“被取消引用，并且如果对象”Z“的引用计数器达到零，则可以将其存储器释放并重新使用。 此后，对于将成为对象“O”的新引用的对象“N”，类似地查询高速缓存硬件。
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公开(公告)号：US20070011220A1
公开(公告)日：2007-01-11
申请号：US11390791
申请日：2006-03-28
IPC分类号： G06F17/15
CPC分类号： G06F7/766
摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.
摘要翻译： 具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。 交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。 通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。 该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。
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8.发明授权公开(公告)号：US06968476B2
公开(公告)日：2005-11-22
申请号：US10180385
申请日：2002-06-26
CPC分类号： G06F9/3842 , G06F9/30174 , G06F9/3834 , G06F9/3863 , G06F9/3885
摘要： The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC instructions in a buffer (CSB)(60) for checkpoint states, whereby a checkpoint state comprises as many buffer slots as registers can be updated by said plurality of CISC instructions and an entry for a Program Counter value associated with the youngest external instruction of said plurality, and to update an Architected Register Array (ARA)(64) with freshly collected register data after determining that no error was detected in the register data after completion of said youngest external instruction of said plurality of external instructions. Handshake synchronization for consistent updates between storage in an L2-cache (66) via a Store Buffer (65) and an Architected Register Array (ARA) (64) is provided which is based on the youngest instruction ID (40) stored in the Checkpoint State Buffer (CSB) (60).
摘要翻译： 本发明涉及从给定检查点内置错误恢复的数据处理系统。 为了对每个周期的多于一个指令进行检查，建议收集用于检查点状态的缓冲器（CSB）（60）中的相应多个CISC / RISC指令执行的预定最大数量的寄存器内容的更新，由此检查点 状态包括与所述多个CISC指令相对应的寄存器可更新的缓冲器槽，以及与所述多个最小外部指令相关联的程序计数器值的条目，并且以新鲜的方式更新建筑物寄存器阵列（ARA）（64） 在完成所述多个外部指令的所述最小外部指令之后确定在所述寄存器数据中没有检测到错误之后，收集的寄存器数据。 提供握手同步，用于通过存储缓冲器（65）和架构化寄存器阵列（ARA）（64）存储在L2高速缓存（66）中的一致更新，其基于存储在检查点中的最年轻的指令ID（40） 状态缓冲区（CSB）（60）。
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公开(公告)号：US09298631B2
公开(公告)日：2016-03-29
申请号：US13524386
申请日：2012-06-15
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
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10.发明授权公开(公告)号：US08891279B2
公开(公告)日：2014-11-18
申请号：US13621328
申请日：2012-09-17
IPC分类号： G11C5/06
CPC分类号： G06F12/0897 , G06F12/0844 , G06F12/0893 , G06F2212/1016 , G06F2212/6042
摘要： A mechanism is provided in a data processing system for enhancing wiring structure for a cache supporting an auxiliary data output. The mechanism splits the data cache into a first data portion and a second data portion. The first data portion provides a first set of data elements and the second data portion provides a second set of data elements. The mechanism connects a first data path to provide the first set of data elements to a primary output and connects a second data path to provide the second set of data elements to the primary output. The mechanism feeds the first data path back into the second data path and feeds the second data path back into the first data path. The mechanism connects a secondary output to the second data path.
摘要翻译： 在用于增强支持辅助数据输出的高速缓存的布线结构的数据处理系统中提供一种机制。 该机制将数据高速缓存分解成第一数据部分和第二数据部分。 第一数据部分提供第一组数据元素，第二数据部分提供第二组数据元素。 该机制连接第一数据路径以将第一组数据元素提供给主输出，并连接第二数据路径以将第二组数据元素提供给主输出。 该机构将第一数据路径馈送回第二数据路径并将第二数据路径馈送回第一数据路径。 该机制将辅助输出连接到第二数据路径。
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