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    Protecting software environment in isolated execution
    2.
    发明申请
    Protecting software environment in isolated execution 有权
    在孤立执行中保护软件环境

    公开(公告)号：US20060206943A1

    公开(公告)日：2006-09-14

    申请号：US11386269

    申请日：2006-03-21

    申请人： Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

    发明人： Carl Ellison ,  Roger Golliver ,  Howard Herbert ,  Derrick Lin ,  Francis McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James Sutton ,  Shreekant Thakkar ,  Millind Mittal

    IPC分类号： H04N7/16

    CPC分类号： G06F21/53 ,  G06F9/468 ,  G06F21/562 ,  G06F21/57 ,  G06F21/74 ,  G06F2221/2105

    摘要： A processing system has a processor that can operate in a normal ring 0 operating mode and one or more higher ring operating modes above the normal ring 0 operating mode. In addition, the processor can operate in an isolated execution mode. A memory in the processing system may include an ordinary memory area that can be accessed from the normal ring 0 operating mode, as well as an isolated memory area that can be accessed from the isolated execution mode but not from the normal ring 0 operating mode. The processing system may also include an operating system (OS) nub, as well as a key generator. The key generator may generate an OS nub key (OSNK) based at least in part on an identification of the OS nub and a master binding key (BK0) of the platform. Other embodiments are described and claimed.

    摘要翻译： 处理系统具有处理器，该处理器可以在正常环0操作模式和高于正常环0操作模式的一个或多个较高环操作模式下操作。 此外，处理器可以在隔离的执行模式下操作。 处理系统中的存储器可以包括可以从正常环0操作模式访问的普通存储器区域以及可以从隔离执行模式而不是从正常环0操作模式访问的隔离存储器区域。 处理系统还可以包括操作系统（OS）nub以及密钥生成器。 密钥生成器可以至少部分地基于OS nub的标识和平台的主绑定密钥（BK 0）来生成OS nub密钥（OSNK）。 描述和要求保护其他实施例。

    Method and Apparatus For A Power-Efficient Framework to Maintain Data Synchronization of a Mobile Personal Computer to Simulate A Connected Scenario
    5.
    发明申请
    Method and Apparatus For A Power-Efficient Framework to Maintain Data Synchronization of a Mobile Personal Computer to Simulate A Connected Scenario 审中-公开
    用于维护移动个人计算机的数据同步的高效框架的方法和装置来模拟连接的场景

    公开(公告)号：US20130013948A1

    公开(公告)日：2013-01-10

    申请号：US13551148

    申请日：2012-07-17

    申请人： Uttam Sengupta ,  Prashant Gandhi ,  Shobhit Varshney ,  Mandar Joshi ,  Shreekant Thakkar

    发明人： Uttam Sengupta ,  Prashant Gandhi ,  Shobhit Varshney ,  Mandar Joshi ,  Shreekant Thakkar

    IPC分类号： G06F1/32

    摘要： An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed.

    摘要翻译： 描述了用于维护移动个人计算机（MPC）的数据同步的功率高效框架的装置和方法。 在一个实施例中，该方法包括在MPC根据睡眠状态操作时检测数据同步唤醒事件。 在唤醒事件之后，禁用至少一个系统资源以提供重新建立网络连接所需的最少数量的系统资源。 在一个实施例中，来自网络服务器的用户数据在MPC上同步，而无需用户干预; 移动平台系统根据睡眠状态恢复操作。 在一个实施例中，根据关于接收到的电子邮件的用户历史简档来编程唤醒警报。 在另一实施例中，数据同步涉及禁用显示器，并且限制系统处理器以降低的频率进行操作。 描述和要求保护其他实施例。

    Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor
    8.
    发明授权
    Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor 有权
    将双向数据复用到主机CPU和协处理器之间的低引脚数总线上的装置和方法

    公开(公告)号：US06434650B1

    公开(公告)日：2002-08-13

    申请号：US09176571

    申请日：1998-10-21

    申请人： Jeff C. Morris ,  Robert J. Greiner ,  Narayana S. Iyer ,  Pranav H. Mehta ,  Shreekant Thakkar ,  Peter Ruscito

    发明人： Jeff C. Morris ,  Robert J. Greiner ,  Narayana S. Iyer ,  Pranav H. Mehta ,  Shreekant Thakkar ,  Peter Ruscito

    IPC分类号： G06F1300

    CPC分类号： G06F13/4291

    摘要： An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line, and a uni-directional clock line, is coupled to the CPU and to the co-processor. The bus supports data transfer between the CPU and the co-processor, including read operations and write operations, where each such operation includes a command phase, a data transfer phase, and an error check phase. The CPU and the co-processor have a dual master slave mode wherein either may be master of the bus, while the other is the slave. The bi-directional data and command bus carries command information from the master to the slave 10 during the command phase, and carries data from the master to the slave during the data transfer phase for a write operation, and from the slave to the master for a read operation. The bi-directional control line specifies the start and end of each transfer. The uni-directional clock line synchronously clocks both the bi-directional data and command bus and the bi-directional control line. Data is transferred a packet at a time; each packet consists of an octet of data, which 15 is transferred during 8 clocks. Flow control need only be applied once for each packet of data, and thus, only once per 8 clocks.

    摘要翻译： 公开了一种用于主机CPU和安全协处理器之间通信的装置和方法，其中具有双向数据和命令总线，双向控制线和单向时钟线的总线被耦合 到CPU和协处理器。 总线支持CPU和协处理器之间的数据传输，包括读操作和写操作，其中每个这样的操作包括命令阶段，数据传输阶段和错误校验阶段。 CPU和协处理器具有双主从模式，其中也可以是总线的主机，而另一个是从机。 双向数据和命令总线在命令阶段将命令信息从主机传送到从机10，并在写操作的数据传输阶段将数据从主机传送到从机，从从机到主机， 一个读操作。 双向控制线指定每次传输的开始和结束。 单向时钟线同时对双向数据和命令总线以及双向控制线进行时钟同步。 数据一次传送一个数据包; 每个数据包由八位字节的数据组成，在8个时钟周期内传输15个数据。 流量控制只需对每个数据包应用一次，因此每8个时钟只需一次。

    METHOD AND APPARATUS FOR EXTERNAL PROCESSOR THERMAL CONTROL
    9.
    发明申请
    METHOD AND APPARATUS FOR EXTERNAL PROCESSOR THERMAL CONTROL 有权
    外部处理器热控制的方法和装置

    公开(公告)号：US20110090640A1

    公开(公告)日：2011-04-21

    申请号：US12980648

    申请日：2010-12-29

    申请人： Eric C. Samson ,  John William Horigan ,  Robert T. Jackson ,  Shreekant Thakkar

    发明人： Eric C. Samson ,  John William Horigan ,  Robert T. Jackson ,  Shreekant Thakkar

    IPC分类号： G06F1/20

    CPC分类号： G06F1/206

    摘要： A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy. The selection policy may be received from a user through a graphical user interface. The selection policy may be based on an action being performed by the computing system.

    摘要翻译： 公开了一种用于节流计算机系统的从属组件以在接收到第一信号时降低计算系统的总体温度的系统和方法。 第一信号可以来自主组件，指示主组件的温度已经超过其阈值温度。 从属组件或主组件可以是中央处理单元，图形存储器和控制器集线器，或中央处理单元存储器控制器集线器。 从组件可以发送第二信号以指示从组件的温度已超过其温度。 然后，主组件将启动主组件的节流以降低计算系统的整体温度。 主部件可以被节流到比从属部件小的程度。 可以将第一组件指定为主组件，并且可以基于选择策略将第二组件指定为从组件。 可以通过图形用户界面从用户接收选择策略。 选择策略可以基于由计算系统执行的动作。