公开(公告)号：US08138028B2

公开(公告)日：2012-03-20

申请号：US11764678

申请日：2007-06-18

申请人： Hsiang Lan Lung ,  Chieh Fang Chen ,  Yi Chou Chen ,  Shih Hung Chen ,  Chung Hon Lam ,  Eric Andrew Joseph ,  Alejandro Gabriel Schrott ,  Matthew J. Breitwisch ,  Geoffrey William Burr ,  Thomas D. Happ ,  Jan Boris Philipp

发明人： Hsiang Lan Lung ,  Chieh Fang Chen ,  Yi Chou Chen ,  Shih Hung Chen ,  Chung Hon Lam ,  Eric Andrew Joseph ,  Alejandro Gabriel Schrott ,  Matthew J. Breitwisch ,  Geoffrey William Burr ,  Thomas D. Happ ,  Jan Boris Philipp

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.

摘要翻译： 用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。 沉积一层电极材料，使其与导电触点阵列可靠地电接触。 蚀刻电极材料以在对应的导电触点上形成电极柱的图案。 接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。 接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。 描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

公开(公告)号：US20100193763A1

公开(公告)日：2010-08-05

申请号：US12727672

申请日：2010-03-19

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L45/00

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US07932507B2

公开(公告)日：2011-04-26

申请号：US12727672

申请日：2010-03-19

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/02

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US20080165569A1

公开(公告)日：2008-07-10

申请号：US11619625

申请日：2007-01-04

申请人： Chieh-Fang Chen ,  Shih-Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih-Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： G11C11/00 ,  H01L21/06 ,  H01L21/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

摘要： A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.

摘要翻译： 存储单元包括第一电极，第二电极和复合材料。 复合材料将第一电极电耦合到第二电极。 此外，复合材料包括相变材料和电阻材料。 响应于向第一和第二电极中的至少一个施加开关信号，相变材料的至少一部分可操作以在基本上结晶相和基本非晶相之间切换。 此外，当相变材料处于基本非晶相时，电阻材料的电阻率低于相变材料的电阻率。

公开(公告)号：US07745807B2

公开(公告)日：2010-06-29

申请号：US11776301

申请日：2007-07-11

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/02

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US20090014704A1

公开(公告)日：2009-01-15

申请号：US11776301

申请日：2007-07-11

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L29/04

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层来形成电流收缩层或用作从底层绝缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US20100019215A1

公开(公告)日：2010-01-28

申请号：US12177435

申请日：2008-07-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of word lines extending in a first direction, and a plurality of bit lines overlying the plurality of word lines and extending in a second direction. A plurality of memory cells are at cross-point locations. Each memory cell comprises a diode having first and second sides aligned with sides of a corresponding word line. Each memory cell also includes a bottom electrode self-centered on the diode, the bottom electrode having a top surface with a surface area less than that of the top surface of the diode. Each of the memory cells includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material underlying and in electrical communication with a corresponding bit line.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括沿第一方向延伸的多个字线和覆盖多个字线并沿第二方向延伸的多个位线。 多个存储单元处于交叉点位置。 每个存储单元包括具有与相应字线的侧面对准的第一和第二侧的二极管。 每个存储单元还包括以二极管为中心的底部电极，底部电极具有表面积小于二极管顶表面的顶表面。 每个存储器单元包括在底部电极的顶表面上的存储器材料条，存储器材料条下面并与相应位线电连通。

公开(公告)号：US08115186B2

公开(公告)日：2012-02-14

申请号：US12498840

申请日：2009-07-07

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： H01L45/144 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1666

摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.

摘要翻译： 通过形成电介质层并在电介质层中构图孔来制造存储单元。 至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。 然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。 图案化介电层的至少一部分保留在最终存储单元中。

公开(公告)号：US20080265234A1

公开(公告)日：2008-10-30

申请号：US11741781

申请日：2007-04-30

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1666

摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.

摘要翻译： 通过形成电介质层并在电介质层中构图孔来制造存储单元。 至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。 然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。 图案化介电层的至少一部分保留在最终存储单元中。

公开(公告)号：US20090294748A1

公开(公告)日：2009-12-03

申请号：US12498840

申请日：2009-07-07

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1666

摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.

摘要翻译： 通过形成电介质层并在电介质层中构图孔来制造存储单元。 至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。 然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。 图案化介电层的至少一部分保留在最终存储单元中。