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    Slot-shielded coplanar strip-line compatible with CMOS processes
    2.
    发明授权
    Slot-shielded coplanar strip-line compatible with CMOS processes 有权
    与CMOS工艺兼容的插槽屏蔽共面带状线

    公开(公告)号：US09087840B2

    公开(公告)日：2015-07-21

    申请号：US12917285

    申请日：2010-11-01

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    IPC分类号： H01L23/14 ,  H01L23/522 ,  H01L23/66 ,  H01L27/06

    CPC分类号： H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66 ,  H01L27/0629 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

    摘要翻译： 带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。 第二多个金属带垂直地与空间重叠。 第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

    Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes
    3.
    发明申请
    Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes 有权
    Slot-Shielded Coplanar Strip-line兼容CMOS工艺

    公开(公告)号：US20120104575A1

    公开(公告)日：2012-05-03

    申请号：US12917285

    申请日：2010-11-01

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    IPC分类号： H01L23/14

    CPC分类号： H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66 ,  H01L27/0629 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

    摘要翻译： 带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。 第二多个金属带垂直地与空间重叠。 第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

    Integrated circuit ground shielding structure
    4.
    发明授权
    Integrated circuit ground shielding structure 有权
    集成电路接地屏蔽结构

    公开(公告)号：US08659126B2

    公开(公告)日：2014-02-25

    申请号：US13313240

    申请日：2011-12-07

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC分类号： H01L23/552

    CPC分类号： H01L23/5227 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

    摘要翻译： 本公开提供了一种集成电路（IC）装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。 该层将第一管芯和第二管芯结合在一起。 本公开还涉及微电子器件。 微电子器件包括包含多个第一互连层的第一管芯。 电感线圈结构设置在第一互连层的子集中。 微电子器件包括包含多个第二互连层的第二管芯。 图案化接地屏蔽（PGS）结构设置在第二互连层的子集中。 微电子器件包括设置在第一和第二裸片之间的底部填充层。 底层填充层包含一个或多个微胶囊。

    INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE
    6.
    发明申请
    INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE 有权
    集成电路接地屏蔽结构

    公开(公告)号：US20130147023A1

    公开(公告)日：2013-06-13

    申请号：US13313240

    申请日：2011-12-07

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC分类号： H01L23/552

    CPC分类号： H01L23/5227 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

    摘要翻译： 本公开提供了一种集成电路（IC）装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。 该层将第一管芯和第二管芯结合在一起。 本公开还涉及微电子器件。 微电子器件包括包含多个第一互连层的第一管芯。 电感线圈结构设置在第一互连层的子集中。 微电子器件包括包含多个第二互连层的第二管芯。 图案化接地屏蔽（PGS）结构设置在第二互连层的子集中。 微电子器件包括设置在第一和第二裸片之间的底部填充层。 底层填充层包含一个或多个微胶囊。

    Voltage-controlled oscillator
    8.
    发明授权
    Voltage-controlled oscillator 有权
    压控振荡器

    公开(公告)号：US08665030B2

    公开(公告)日：2014-03-04

    申请号：US13325442

    申请日：2011-12-14

    申请人： Ying-Ta Lu ,  Hsien-Yuan Liao ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    发明人： Ying-Ta Lu ,  Hsien-Yuan Liao ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC分类号： H03B5/12

    CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1852

    摘要： A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit.

    摘要翻译： 压控振荡器电路包括第一晶体管，第二晶体管，第一谐振器电路，第二谐振器电路，第一电流路径和第二电流路径。 第一晶体管的漏极耦合到第二晶体管的栅极和第一谐振器电路的第一端。 第一晶体管的源极耦合到第一电流路径和第二谐振器电路的第一端。 第二晶体管的漏极耦合到第一晶体管的栅极和第一谐振器电路的第二端。 第二晶体管的源极耦合到第二电流路径和第二谐振器电路的第二端。

    Gated-varactors
    9.
    发明授权
    Gated-varactors 有权
    门控变容二极管

    公开(公告)号：US08609479B2

    公开(公告)日：2013-12-17

    申请号：US13595667

    申请日：2012-08-27

    申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin Wei Kuo ,  Sally Liu

    发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin Wei Kuo ,  Sally Liu

    IPC分类号： H01L21/02

    CPC分类号： H01L29/93 ,  H01L29/7391 ,  H01L29/94

    摘要： In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.

    摘要翻译： 在至少一个实施例中，制造变容二极管的方法包括在衬底上形成阱。 该井具有第一种掺杂。 在阱中形成第一源极区域和第二源极区域，并且第一源极区域和第二源极区域具有第二类型掺杂。 在阱中形成漏极区，漏区具有第一类掺杂。 在漏极区域和第一源极区域之间的阱上形成第一栅极区域。 此外，在漏极区域和第二源极区域之间的阱之上形成第二栅极区域。

    Filter using a waveguide structure
    10.
    发明授权
    Filter using a waveguide structure 有权
    使用波导结构滤波

    公开(公告)号：US08946832B2

    公开(公告)日：2015-02-03

    申请号：US12701170

    申请日：2010-02-05

    申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin-Wei Kuo

    发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin-Wei Kuo

    IPC分类号： H01L29/84 ,  H01P1/203

    CPC分类号： H01P1/20345

    摘要： A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports.

    摘要翻译： 代表性滤波器包括具有顶表面的绝缘体上硅衬底，位于绝缘体上硅衬底的顶表面上方的金属屏蔽以及位于金属屏蔽上方的带通滤波器器件。 带通滤波器装置包括位于第一和第二端口之间的第一端口，第二端口和耦合金属。