公开(公告)号：US09147020B2

公开(公告)日：2015-09-29

申请号：US13091803

申请日：2011-04-21

申请人： Hsiu-Ying Cho ,  Jiun-Kai Huang ,  Wen-Sheh Huang ,  Chin-Wei Kuo ,  Min-Chie Jeng

发明人： Hsiu-Ying Cho ,  Jiun-Kai Huang ,  Wen-Sheh Huang ,  Chin-Wei Kuo ,  Min-Chie Jeng

IPC分类号： H01L23/522 ,  G06F17/50 ,  H01L21/66

CPC分类号： G06F17/5036 ,  H01L22/34

摘要： A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.

摘要翻译： 一种方法包括模拟具有第一长度的第一传输线的特性，以及模拟具有大于第一长度的第二长度的第二传输线的特性。 然后对第一传输线的特性和第二传输线的特性执行计算，以产生具有等于第二长度和第一长度的差的长度的第三传输线的固有特性。

公开(公告)号：US09087838B2

公开(公告)日：2015-07-21

申请号：US13280786

申请日：2011-10-25

申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

IPC分类号： H01L23/52 ,  H01L21/02 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02

CPC分类号： H01L23/5222 ,  H01F17/0013 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/552 ,  H01L23/642 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有集成电路（IC）器件的半导体衬底; 布置在半导体衬底上并与IC器件耦合的互连结构; 以及设置在半导体衬底上并集成在互连结构中的变压器。 变压器包括第一导电特征; 与所述第一导电特征电感耦合的第二导电特征; 电连接到第一导电特征的第三导电特征; 以及电连接到第二导电特征的第四导电特征。 第三和第四导电特征被设计和配置为电容耦合以增加变压器的耦合系数。

公开(公告)号：US08674883B2

公开(公告)日：2014-03-18

申请号：US13114828

申请日：2011-05-24

申请人： Hsiao-Tsung Yen ,  Jhe-Ching Lu ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Min-Chie Jeng

发明人： Hsiao-Tsung Yen ,  Jhe-Ching Lu ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Min-Chie Jeng

IPC分类号： H01Q1/38

CPC分类号： H01Q1/50 ,  G06F17/5068 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/074 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/1421 ,  H01L2924/1461 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q5/357 ,  H01Q9/0421 ,  H01Q9/0442 ,  H01Q9/145 ,  Y10T29/49016 ,  H01L2924/00

摘要： An antenna includes a substrate and a top plate disposed over the substrate. At least one feed line is connected to the top plate, and each feed line comprises a first through-silicon via (TSV) structure passing through the substrate. At least one ground line is connected to the top plate, and each ground line comprises a second TSV structure passing through the substrate. The top plate is electrically conductive, and the at least one feed line is arranged to carry a radio frequency signal. The at least one ground line is arranged to be coupled to a ground.

摘要翻译： 天线包括衬底和设置在衬底上的顶板。 至少一个进料管线连接到顶板，并且每个进料管线包括穿过基材的第一穿硅通孔（TSV）结构。 至少一个接地线连接到顶板，并且每个接地线包括穿过衬底的第二TSV结构。 顶板是导电的，并且至少一个馈线布置成承载射频信号。 所述至少一个接地线被布置成联接到地面。

公开(公告)号：US20130277794A1

公开(公告)日：2013-10-24

申请号：US13841577

申请日：2013-03-15

申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng-Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng-Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

IPC分类号： H01L23/60

CPC分类号： H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.

摘要翻译： 一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。 包括第二垫的工件被结合到模具。 第一多个微凸块在第一和第二焊盘之间串联电耦合。 多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。 微凸块与模具和工件结合。 第二焊盘电耦合到微凸起。

公开(公告)号：US20130246990A1

公开(公告)日：2013-09-19

申请号：US13419959

申请日：2012-03-14

申请人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Chin-Wei Kuo

发明人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Chin-Wei Kuo

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other.

摘要翻译： 计算机实现的系统包括被编程为分析电路以确定电路对输入射频（RF）信号的响应的处理器，用于设计，制造和测试电路中的至少一个。 中介层模型有形地体现在待处理器访问的非暂时机器可读存储介质中。 内插器模型由计算机处理以将表示通过（TSV）的基板的响应的数据输出到射频（RF）信号。 内插器模型包括多个TSV模型。 每个TSV模型都有相应的三端口网络。 每个三端口网络的一个端口是浮动节点。 每个三端口网络的浮动节点彼此连接。

公开(公告)号：US20130234305A1

公开(公告)日：2013-09-12

申请号：US13415906

申请日：2012-03-09

申请人： Yu-Ling LIN ,  Hsiao-Tsung YEN ,  Feng Wei KUO ,  Ho-Hsiang CHEN ,  Chin-Wei KUO

发明人： Yu-Ling LIN ,  Hsiao-Tsung YEN ,  Feng Wei KUO ,  Ho-Hsiang CHEN ,  Chin-Wei KUO

IPC分类号： H01L23/58 ,  H01L21/28

CPC分类号： H01L23/60 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/66 ,  H01L25/0657 ,  H01L2223/6627 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications.

摘要翻译： 用于半导体RF和无线电路的传输线结构及其形成方法。 传输线结构包括具有包括第一衬底，第一绝缘层和接地平面的第一裸片的实施例，以及包括第二衬底，第二绝缘层和信号传输线的第二裸片。 第二管芯可以位于第一管芯的上方并与之隔开。 在第一管芯的接地面和第二管芯的信号传输线之间设置底部填充物。 总的来说，第一和第二模具和底部填充物的接地平面和传输线形成紧凑的传输线结构。 在一些实施例中，传输线结构可用于微波应用。

公开(公告)号：US08502338B2

公开(公告)日：2013-08-06

申请号：US12878803

申请日：2010-09-09

申请人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Chin-Wei Kuo ,  Sally Liu

发明人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Chin-Wei Kuo ,  Sally Liu

IPC分类号： H01L29/00

CPC分类号： H01L27/0296 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/60 ,  H01L29/861 ,  H01L2223/6622 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

摘要： A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.

摘要翻译： 一种器件包括第一导电类型的半导体衬底，其中半导体衬底包括与第一表面相对的第一表面和第二表面。 贯穿基板通孔（TSV）从半导体基板的第一表面延伸到第二表面。 与第一导电类型相反的第二导电类型的阱区域包围TSV，并且从半导体衬底的第一表面延伸到第二表面。

公开(公告)号：US20130032799A1

公开(公告)日：2013-02-07

申请号：US13197602

申请日：2011-08-03

申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Victor Chih Yuan Chang ,  Min-Chie Jeng

发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Victor Chih Yuan Chang ,  Min-Chie Jeng

IPC分类号： H01L23/528 ,  H01L21/66

CPC分类号： G01R31/2644 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.

摘要翻译： 一种方法包括在具有至少两个通过衬底通孔（TSV）的衬底上提供多个测试结构，用于对包括至少两个TSV的被测器件（DUT）的固有特性的测量进行解嵌入; 测量包括与长度为L的传输线耦合的两个焊盘的衬底上的第一和第二测试结构的固有特性[L] 使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解焊盘和传输线的固有特性; 使用焊盘和传输线的固有特性来解嵌第三和第四测试结构的测量; 并且对于BM_L和BM_LX使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解TSV的固有特性。

公开(公告)号：US20120153433A1

公开(公告)日：2012-06-21

申请号：US12974896

申请日：2010-12-21

申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

IPC分类号： H01L23/552 ,  H01L23/00

CPC分类号： H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.

摘要翻译： 一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。 包括第二垫的工件被结合到模具。 第一多个微凸块在第一和第二焊盘之间串联电耦合。 多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。 微凸块与模具和工件结合。 第二焊盘电耦合到微凸起。

公开(公告)号：US20120139867A1

公开(公告)日：2012-06-07

申请号：US13293467

申请日：2011-11-10

申请人： Sean CHANG ,  Chii-How CHANG ,  Chin-Wei KUO

发明人： Sean CHANG ,  Chii-How CHANG ,  Chin-Wei KUO

IPC分类号： G06F3/044

CPC分类号： G06F3/044 ,  G06F3/0416

摘要： A capacitive touch apparatus includes a first touch unit, a first voltage difference retrieving unit, a first feedback signal generating unit, and a control unit. The first touch unit has a touch substrate and a first conductive layer. The first voltage difference retrieving unit is electrically connected with the first conductive layer and outputs a first voltage signal and a second voltage signal. The first feedback signal generating unit outputs a first feedback signal according to the variation of the voltage difference between the first voltage signal and the second voltage signal. The control unit receives the first feedback signal for computing the touch position and outputs a power signal to the first voltage difference retrieving unit. Hence, the capacitive touch apparatus improves the sensing speed and reduces the manufacturing cost by the simple circuit design.

摘要翻译： 电容式触摸装置包括第一触摸单元，第一电压差检索单元，第一反馈信号生成单元和控制单元。 第一触摸单元具有触摸基板和第一导电层。 第一电压差检索单元与第一导电层电连接并输出第一电压信号和第二电压信号。 第一反馈信号发生单元根据第一电压信号和第二电压信号之间的电压差的变化输出第一反馈信号。 控制单元接收用于计算触摸位置的第一反馈信号，并将功率信号输出到第一电压差检索单元。 因此，电容式触摸装置通过简单的电路设计提高了感测速度并降低了制造成本。