公开(公告)号：US06211006B1

公开(公告)日：2001-04-03

申请号：US09435031

申请日：1999-11-05

申请人： Hsin-Chuan Tsai ,  Yi-Nan Chen ,  Pei-Ing Paul Lee

发明人： Hsin-Chuan Tsai ,  Yi-Nan Chen ,  Pei-Ing Paul Lee

IPC分类号： H01L218242

CPC分类号： H01L27/1087

摘要： The present invention relates to a method of forming a trench-type capacitor. More particularly, the plate areas of the trench-type capacitor are increased according to the present invention. The method of this invention comprises the steps of: providing a semiconductor substrate; forming a first trench in the semiconductor substrate, wherein the first trench has a first predetermined depth in the semiconductor substrate; forming first spacers on the side-walls of the first trench, wherein the first spacers include second spacers formed at the bottom of the first trench and third spacers exposed to the air; forming a second trench by aligning the semiconductor substrate with masks of the first spacers and etching the semiconductor substrate to a second predetermined depth; forming a first conducting layer by doping ions into the semiconductor substrate in the second trench; forming an oxide layer on the surface of the first conducting layer by oxidation, wherein the thickness of the oxide layer is less than that of the first conducting layer; forming a second conducting layer by removing the oxide layer, removing the first spacers; forming a dielectric layer upon the second conducting layer; and forming a third conducting layer upon the dielectric layer.

摘要翻译： 本发明涉及一种形成沟槽型电容器的方法。 更具体地，根据本发明，沟槽型电容器的板区域增加。 本发明的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底中形成第一沟槽，其中所述第一沟槽在所述半导体衬底中具有第一预定深度; 在所述第一沟槽的侧壁上形成第一间隔物，其中所述第一间隔物包括形成在所述第一沟槽的底部的第二间隔物和暴露于空气的第三间隔物; 通过将半导体衬底与第一间隔物的掩模对准并将半导体衬底蚀刻到第二预定深度来形成第二沟槽; 通过在第二沟槽中将离子掺杂到半导体衬底中形成第一导电层; 通过氧化在所述第一导电层的表面上形成氧化物层，其中所述氧化物层的厚度小于所述第一导电层的厚度; 通过去除所述氧化物层来形成第二导电层，去除所述第一间隔物; 在所述第二导电层上形成电介质层; 以及在所述电介质层上形成第三导电层。

公开(公告)号：US6117726A

公开(公告)日：2000-09-12

申请号：US326668

申请日：1999-06-07

申请人： Hsin-Chuan Tsai ,  Pei-Ing Paul Lee

发明人： Hsin-Chuan Tsai ,  Pei-Ing Paul Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867

摘要： A method of making a trench capacitor including the following steps: forming a first trench of predetermined depth into a semiconductor substrate; forming an electrode plate on the side-wall of a bottom of the first trench; forming a dielectric layer on the electrode plate; forming a first conductive portion on the dielectric layer, wherein the first conductive portion fills the bottom of the first trench to form a second trench; forming an insulation layer to fill the bottom portion of the second trench to make a third trench in the second trench; forming a conductive spacer along the side-wall of the third trench; etching the insulation layer using the conductive spacer as a mask to form a forth trench; and then filling the forth trench with a conductive material.

摘要翻译： 一种制造沟槽电容器的方法，包括以下步骤：将预定深度的第一沟槽形成为半导体衬底; 在所述第一沟槽的底部的侧壁上形成电极板; 在所述电极板上形成电介质层; 在所述电介质层上形成第一导电部分，其中所述第一导电部分填充所述第一沟槽的底部以形成第二沟槽; 形成绝缘层以填充所述第二沟槽的底部以在所述第二沟槽中形成第三沟槽; 沿着所述第三沟槽的侧壁形成导电间隔物; 使用导电间隔物作为掩模蚀刻绝缘层以形成第四沟槽; 然后用导电材料填充第四沟槽。

公开(公告)号：US5872390A

公开(公告)日：1999-02-16

申请号：US911542

申请日：1997-08-14

申请人： Pei-Ing Paul Lee ,  William Alan Klaasen ,  Alexander Mitwalsky

发明人： Pei-Ing Paul Lee ,  William Alan Klaasen ,  Alexander Mitwalsky

IPC分类号： H01H85/00 ,  H01L21/82 ,  H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L2924/0002

摘要： A fuse window structure and method for forming the same for a semiconductor device with a fuse and a cutting site on the fuse, the structure having (1) a first oxide region substantially in register with the cutting site, the first oxide region having a first thickness, (2) a second oxide region substantially in register with a first land generally surrounding the cutting site, the first land generally in register with the fuse, the second region having a second thickness, and (3) a third oxide region substantially in register with a second land generally surrounding the fuse, the third region having a third thickness different than the first thickness. Different fuse window structures are formed by using etch stops with different configurations, each configuration differing with regard to coverage of the three oxide regions.

摘要翻译： 一种用于在熔丝上具有熔丝和切割部位的半导体器件形成熔丝窗结构和方法，所述结构具有（1）与所述切割部位基本上对准的第一氧化物区域，所述第一氧化物区域具有第一 厚度，（2）基本上与通常围绕切割位置的第一焊盘对准的第二氧化物区域，第一焊盘通常与熔丝对准，第二区域具有第二厚度，以及（3）基本上在 与通常围绕熔丝的第二焊盘对准，第三区域具有不同于第一厚度的第三厚度。 通过使用具有不同配置的蚀刻停止件形成不同的熔丝窗结构，每个配置关于三个氧化物区域的覆盖范围不同。

公开(公告)号：US5798301A

公开(公告)日：1998-08-25

申请号：US841030

申请日：1997-04-29

申请人： Pei-Ing Paul Lee ,  Bernd Vollmer ,  Darryl Restaino ,  Bill Klaasen

发明人： Pei-Ing Paul Lee ,  Bernd Vollmer ,  Darryl Restaino ,  Bill Klaasen

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/283

CPC分类号： H01L21/76843 ,  H01L21/28512 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002

摘要： A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C. and 550.degree. C. The titanium layer and the adjacent titanium nitride layer below the aluminum alloy layer provide the interconnect structure with low resistivity and prevent alloy spiking of the base substrate. As a result, a multilayer interconnect structure provided that has improved electromigration reliability and a low resistance, thereby enabling more dense applications within an integrated circuit.

摘要翻译： 一种用于半导体集成电路的多层互连结构，包括钛基底层，第二氮化钛层，第三层铝合金和顶层氮化钛。 包含在多层互连结构内的所有层通过原位沉积沉积在超高真空沉积系统中。 沉积在沉积系统中的不同层连续进行，而不会破坏真空。 尽管多层互连结构中的每个层都沉积在具有多个沉积室的集成超高真空沉积系统内，但不同层的沉积在不同的温度下进行。 通过在超过300℃，优选350℃至550℃的温度下沉积铝合金层，由铝合金的电迁移引起的多层互连结构的电迁移故障的时间大大增加。 C.在铝合金层下面的钛层和相邻的氮化钛层提供具有低电阻率的互连结构并防止基底衬底的合金尖峰。 结果，提供了具有改善的电迁移可靠性和低电阻的多层互连结构，从而使集成电路内的应用更加密集。

公开(公告)号：US5641992A

公开(公告)日：1997-06-24

申请号：US513494

申请日：1995-08-10

申请人： Pei-Ing Paul Lee ,  Bernd Vollmer ,  Darryl Restaino ,  Bill Klaasen

发明人： Pei-Ing Paul Lee ,  Bernd Vollmer ,  Darryl Restaino ,  Bill Klaasen

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/28512 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002

摘要： A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C. and 550.degree. C. The titanium layer and the adjacent titanium nitride layer below the aluminum alloy layer provide the interconnect structure with low resistivity and prevent alloy spiking of the base substrate. As a result, a multilayer interconnect structure provided that has improved electromigration reliability and a low resistance, thereby enabling more dense applications within an integrated circuit.

摘要翻译： 一种用于半导体集成电路的多层互连结构，包括钛基底层，第二氮化钛层，第三层铝合金和顶层氮化钛。 包含在多层互连结构内的所有层通过原位沉积沉积在超高真空沉积系统中。 沉积在沉积系统中的不同层连续进行，而不会破坏真空。 尽管多层互连结构中的每个层都沉积在具有多个沉积室的集成超高真空沉积系统内，但不同层的沉积在不同的温度下进行。 通过在超过300℃，优选350℃至550℃的温度下沉积铝合金层，由铝合金的电迁移引起的多层互连结构的电迁移故障的时间大大增加。 C.在铝合金层下面的钛层和相邻的氮化钛层提供具有低电阻率的互连结构并防止基底衬底的合金尖峰。 结果，提供了具有改善的电迁移可靠性和低电阻的多层互连结构，从而使集成电路内的应用更加密集。