公开(公告)号：US20060189153A1

公开(公告)日：2006-08-24

申请号：US11406595

申请日：2006-04-19

申请人： Daniel Edelstein ,  Alfred Grill ,  Vishnubhai Patel ,  Darryl Restaino

发明人： Daniel Edelstein ,  Alfred Grill ,  Vishnubhai Patel ,  Darryl Restaino

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834

摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

公开(公告)号：US20060134911A1

公开(公告)日：2006-06-22

申请号：US10905230

申请日：2004-12-22

申请人： Darryl Restaino ,  Donald Canaperi ,  Judith Rubino ,  Sean Smith ,  Richard Henry ,  James Fluegel ,  Mahadevaiyer Krishnan

发明人： Darryl Restaino ,  Donald Canaperi ,  Judith Rubino ,  Sean Smith ,  Richard Henry ,  James Fluegel ,  Mahadevaiyer Krishnan

IPC分类号： H01L21/44

CPC分类号： H01L21/288 ,  C23C18/1241 ,  C23C18/1607 ,  C23C18/1608 ,  C23C18/1844 ,  C23C18/50 ,  H01L21/76849 ,  H01L21/76874 ,  H05K3/244 ,  H05K2203/0716 ,  H05K2203/072

摘要： A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.

摘要翻译： 一种以可再生的方式对铜上的CoWP合金进行无电镀的方法，该方法对于可制造的工艺是有效的。 在该方法中，通过乙酸钯，乙酸和氯化物的水性接种溶液将铜（Pd）种子层沉积在铜上。 此后，应用络合溶液以除去吸附在除铜之外的表面上的任何Pd离子。 最后，将铜（Co），钨（W）和磷（P）的电镀溶液施加到铜上，以便在Pd种子和铜上沉积CoWP层。

公开(公告)号：US06806182B2

公开(公告)日：2004-10-19

申请号：US10137274

申请日：2002-05-01

申请人： Darryl Restaino ,  Shahab Siddiqui ,  Erdem Kaltalioglu ,  Delores Bennett ,  Chih-Chih Liu ,  Hsueh-Chung Chen ,  Tong-Yu Chen ,  Gwo-Shii Yang ,  Chiung-Sheng Hsiung

发明人： Darryl Restaino ,  Shahab Siddiqui ,  Erdem Kaltalioglu ,  Delores Bennett ,  Chih-Chih Liu ,  Hsueh-Chung Chen ,  Tong-Yu Chen ,  Gwo-Shii Yang ,  Chiung-Sheng Hsiung

IPC分类号： H01L214763

CPC分类号： H01L21/02252 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834

摘要： Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

摘要翻译： 在覆盖有机层间介质之前，将粘合促进剂施加到覆盖层和粘附促进剂的氧化之后，减少了体现多层金属和有机层间电介质的半导体晶片的热循环过程中的电阻问题。

公开(公告)号：US20070148958A1

公开(公告)日：2007-06-28

申请号：US11499220

申请日：2006-08-04

申请人： Lawrence Clevenger ,  Stefanie Chiras ,  Timothy Dalton ,  James Demarest ,  Derren Dunn ,  Chester Dziobkowski ,  Philip Flaitz ,  Michael Lane ,  James Lloyd ,  Darryl Restaino ,  Thomas Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Stefanie Chiras ,  Timothy Dalton ,  James Demarest ,  Derren Dunn ,  Chester Dziobkowski ,  Philip Flaitz ,  Michael Lane ,  James Lloyd ,  Darryl Restaino ,  Thomas Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20060202311A1

公开(公告)日：2006-09-14

申请号：US10906815

申请日：2005-03-08

申请人： Son Nguyen ,  Sarah Lane ,  Eric Liniger ,  Kensaku Ida ,  Darryl Restaino

发明人： Son Nguyen ,  Sarah Lane ,  Eric Liniger ,  Kensaku Ida ,  Darryl Restaino

IPC分类号： H01L23/58 ,  H01L21/469 ,  H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

摘要翻译： 具有约3.0或更小的有效介电常数k的低k电介质堆叠，其中通过将至少一个纳米层引入电介质叠层来提高堆叠的机械性能。 在不显着增加叠层内的膜的介电常数并且不需要使本发明的电介质叠层进行任何后处理步骤的情况下，实现机械性能的改善。 具体地，本发明提供了一种低k电介质堆叠，其包含至少一个低k​​电介质材料和存在于至少一个低k​​电介质材料内的至少一个纳米层。

公开(公告)号：US20050230831A1

公开(公告)日：2005-10-20

申请号：US10827693

申请日：2004-04-19

申请人： Lawrence Clevenger ,  Stefanie Chiras ,  Timothy Dalton ,  James Demarest ,  Derren Dunn ,  Chester Dziobkowski ,  Philip Flaitz ,  Michael Lane ,  James Lloyd ,  Darryl Restaino ,  Thomas Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Stefanie Chiras ,  Timothy Dalton ,  James Demarest ,  Derren Dunn ,  Chester Dziobkowski ,  Philip Flaitz ,  Michael Lane ,  James Lloyd ,  Darryl Restaino ,  Thomas Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20050087490A1

公开(公告)日：2005-04-28

申请号：US10695374

申请日：2003-10-28

申请人： Mark Chace ,  Jeffrey Hedrick ,  Habib Hichri ,  Keith Pope ,  Jia Lee ,  Kelly Malone ,  Kenneth McCullough ,  Wayne Moreau ,  Darryl Restaino ,  Shahab Siddiqui

发明人： Mark Chace ,  Jeffrey Hedrick ,  Habib Hichri ,  Keith Pope ,  Jia Lee ,  Kelly Malone ,  Kenneth McCullough ,  Wayne Moreau ,  Darryl Restaino ,  Shahab Siddiqui

IPC分类号： B01D11/04 ,  B01D11/00

CPC分类号： B01D11/0407

摘要： A process of removing impurities from a cured low dielectric constant organic polymeric film disposed on a semiconductor device. The process involves disposing a low dielectric constant curable organic polymeric film on an electrically conductive surface of a semiconductor device. The organic polymeric film is cured on the semiconductor device and thereupon contacted with supercritical carbon dioxide, optionally in the presence of at least one cosolvent.

摘要翻译： 从设置在半导体器件上的固化的低介电常数有机聚合物膜去除杂质的方法。 该方法包括将低介电常数可固化有机聚合物膜设置在半导体器件的导电表面上。 有机聚合物膜在半导体器件上固化，随后与超临界二氧化碳接触，任选地在至少一种助溶剂的存在下。

公开(公告)号：US20050059258A1

公开(公告)日：2005-03-17

申请号：US10662022

申请日：2003-09-12

申请人： Daniel Edelstein ,  Alfred Grill ,  Vishnubhai Patel ,  Darryl Restaino

发明人： Daniel Edelstein ,  Alfred Grill ,  Vishnubhai Patel ,  Darryl Restaino

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834

摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

摘要翻译： 半导体器件结构和制造方法包括具有顶部第一层的衬底; 位于所述第一层顶部的第二薄过渡层; 以及位于所述过渡层顶部的第三层，其中所述第二薄过渡层在所述结构的所述第一和第三层之间提供强粘合力和内聚强度。 此外，半导体器件结构和制造方法包括绝缘结构，其包括多个介电层和导电层，其中设置有各自的过渡键合层以增强不同层之间的界面强度。 此外，电子器件结构包括绝缘和导电材料层，作为后端线（“BEOL”）布线结构中的层间或层间电介质，其中不同对的介电膜之间的界面强度由 薄的中间过渡粘合层。

公开(公告)号：US5798301A

公开(公告)日：1998-08-25

申请号：US841030

申请日：1997-04-29

申请人： Pei-Ing Paul Lee ,  Bernd Vollmer ,  Darryl Restaino ,  Bill Klaasen

发明人： Pei-Ing Paul Lee ,  Bernd Vollmer ,  Darryl Restaino ,  Bill Klaasen

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/283

CPC分类号： H01L21/76843 ,  H01L21/28512 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002

摘要： A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C. and 550.degree. C. The titanium layer and the adjacent titanium nitride layer below the aluminum alloy layer provide the interconnect structure with low resistivity and prevent alloy spiking of the base substrate. As a result, a multilayer interconnect structure provided that has improved electromigration reliability and a low resistance, thereby enabling more dense applications within an integrated circuit.

摘要翻译： 一种用于半导体集成电路的多层互连结构，包括钛基底层，第二氮化钛层，第三层铝合金和顶层氮化钛。 包含在多层互连结构内的所有层通过原位沉积沉积在超高真空沉积系统中。 沉积在沉积系统中的不同层连续进行，而不会破坏真空。 尽管多层互连结构中的每个层都沉积在具有多个沉积室的集成超高真空沉积系统内，但不同层的沉积在不同的温度下进行。 通过在超过300℃，优选350℃至550℃的温度下沉积铝合金层，由铝合金的电迁移引起的多层互连结构的电迁移故障的时间大大增加。 C.在铝合金层下面的钛层和相邻的氮化钛层提供具有低电阻率的互连结构并防止基底衬底的合金尖峰。 结果，提供了具有改善的电迁移可靠性和低电阻的多层互连结构，从而使集成电路内的应用更加密集。

公开(公告)号：US07691736B2

公开(公告)日：2010-04-06

申请号：US11352047

申请日：2006-02-10

申请人： Michael Beck ,  John A. Fitzsimmons ,  Karl Hornik ,  Darryl Restaino

发明人： Michael Beck ,  John A. Fitzsimmons ,  Karl Hornik ,  Darryl Restaino

IPC分类号： H01L21/4763

CPC分类号： H01L21/3105 ,  H01L21/02074 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76834

摘要： Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (≦2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

摘要翻译： 本发明的实施例提供一种具有介电材料的半导体器件及其制造方法。 一种方法包括ILD表面的短（＆nlE; 2秒）闪光激活，随后在活化的ILD表面上流动诸如硅烷DEMS之类的前体。 前体与活化的ILD表面反应，从而有选择地保护ILD表面。 受保护的ILD表面耐等离子体处理损伤。 受保护的ILD表面消除了使用硬掩模来保护电介质免受等离子体损伤的要求。