公开(公告)号：US06665216B1

公开(公告)日：2003-12-16

申请号：US10202245

申请日：2002-07-23

申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

IPC分类号： G11C700

CPC分类号： G11C16/28 ,  G11C7/062

摘要： A system for reading data in a memory cell includes three comparators, each of which has two inputs. A first reference cell having a low reference voltage is coupled to one input of the first comparator. A second reference cell having a high reference voltage is coupled to one input of the second comparator. A memory cell having a memory cell voltage is coupled to the other input of the first and second comparators. One input of the third comparator is coupled to the first comparator's output signal, which includes a difference voltage between the memory cell voltage and the low reference voltage. The other input of the third comparator is coupled to the second comparator's output signal, which includes a difference voltage between the memory cell voltage and the high reference voltage. A method and apparatus for reading data in a memory cell also are described.

摘要翻译： 用于读取存储器单元中的数据的系统包括三个比较器，每个比较器具有两个输入。 具有低参考电压的第一参考单元耦合到第一比较器的一个输入端。 具有高参考电压的第二参考单元耦合到第二比较器的一个输入端。 具有存储单元电压的存储单元耦合到第一和第二比较器的另一个输入端。 第三比较器的一个输入耦合到第一比较器的输出信号，其包括存储单元电压和低参考电压之间的差电压。 第三比较器的另一输入端耦合到第二比较器的输出信号，其包括存储单元电压和高参考电压之间的差电压。 还描述了一种用于在存储器单元中读取数据的方法和装置。

公开(公告)号：US06845052B1

公开(公告)日：2005-01-18

申请号：US10250040

申请日：2003-05-30

申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

IPC分类号： G11C7/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C16/28 ,  G11C2207/2227

摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.

摘要翻译： 本发明提供了一种用于非易失性存储器的双参考单元感测方案。 高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。 两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。 双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。 双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

公开(公告)号：US06421267B1

公开(公告)日：2002-07-16

申请号：US09840709

申请日：2001-04-24

申请人： Nai-Ping Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

发明人： Nai-Ping Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

IPC分类号： G11C1134

CPC分类号： G11C16/3495 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/16

摘要： A memory array architecture includes a plurality of memory cells formed into rows and columns. A plurality of bit lines is connected to the memory cells through select transistors. By disposing adjacent bit lines into different metal layers or alternatively interlocating adjacent bit lines, the coupling effect between bit lines can be effectively reduced, and thus can improve reading speed of memory while performing read operation.

摘要翻译： 存储器阵列结构包括形成行和列的多个存储单元。 多个位线通过选择晶体管连接到存储单元。 通过将相邻的位线布置在不同的金属层中或者可选地相互位置相邻的位线，可以有效地减少位线之间的耦合效应，从而可以在执行读取操作时提高存储器的读取速度。

公开(公告)号：US06396753B1

公开(公告)日：2002-05-28

申请号：US09826497

申请日：2001-04-05

申请人： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Tu-Shun Chen ,  Ho-Chun Liou

发明人： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Tu-Shun Chen ,  Ho-Chun Liou

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2207/104

摘要： A method and structure for testing embedded flash memory including a memory array and a logic element. A control transistor is disposed and is connected between a sense amplifier and an I/O buffer in the memory array, and a speed control pin connected to the logic element in one terminal is coupled to the gate terminal of the control transistor in the other terminal to switch the control transistor on or off. Turning off the control transistor after a test time by the speed control pin closes the channel between the sense amplifier and I/O buffer, and an output signal from the memory array to a test system connected to the logic element is detected with the test system to determine an access time of the memory array.

摘要翻译： 一种用于测试包括存储器阵列和逻辑元件的嵌入式闪速存储器的方法和结构。 控制晶体管被设置并连接在存储器阵列中的读出放大器和I / O缓冲器之间，并且连接到一个端子中的逻辑元件的速度控制引脚耦合到另一个端子中的控制晶体管的栅极端子 开关控制晶体管。 通过速度控制引脚在测试时间后关闭控制晶体管，关闭读出放大器和I / O缓冲器之间的通道，并从测试系统检测到从存储器阵列到连接到逻辑元件的测试系统的输出信号 以确定存储器阵列的访问时间。

公开(公告)号：US06563735B1

公开(公告)日：2003-05-13

申请号：US10117148

申请日：2002-04-04

申请人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

发明人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

IPC分类号： G11C1604

CPC分类号： G11C16/0491

摘要： A NOR-structured semiconductor memory device with a novel configuration of bit line connection is disclosed. The NOR-structured semiconductor memory device comprises a semiconductor memory cell array electrically connected to a plurality of bit lines. The plurality of bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main bit line through at least two bit line transistors, respectively. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively. During a programming or data reading operation, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage or sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device successfully prevents the programming disturbance or correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.

摘要翻译： 公开了具有位线连接的新颖结构的NOR结构的半导体存储器件。 NOR结构的半导体存储器件包括电连接到多个位线的半导体存储单元阵列。 多个位线被分成至少四个位线组。 每个位线组的至少两个位线分别通过至少两个位线晶体管耦合到主位线。 此外，NOR结构半导体存储器件的位线被布置成使得其中至少四个相邻的位线分别从四个不同的位线组中选择并且分别耦合到四个不同的主位线。 在编程或数据读取操作期间，四个相邻位线中的两个相邻位线被提供有编程电压或感测电流，而另外两个相邻位线接地。 因此，由于没有形成泄漏电流路径，所以NOR结构的半导体存储器件成功地防止了编程干扰或者以高速正确地确定存储在存储单元中的数据。

公开(公告)号：US07649772B2

公开(公告)日：2010-01-19

申请号：US11779951

申请日：2007-07-19

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.

摘要翻译： 一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。 首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。 接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

公开(公告)号：US20090021994A1

公开(公告)日：2009-01-22

申请号：US11779951

申请日：2007-07-19

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.

摘要翻译： 一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。 首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。 接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

公开(公告)号：US08717813B2

公开(公告)日：2014-05-06

申请号：US13308266

申请日：2011-11-30

申请人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

发明人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC分类号： G11C11/34

CPC分类号： G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

公开(公告)号：US20130242665A1

公开(公告)日：2013-09-19

申请号：US13536555

申请日：2012-06-28

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14 ,  G11C29/34 ,  G11C2029/2602

摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

摘要翻译： 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

公开(公告)号：US20120262988A1

公开(公告)日：2012-10-18

申请号：US13308301

申请日：2011-11-30

申请人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

发明人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC分类号： G11C16/10

CPC分类号： G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.

摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，描述了一种闪存器件，其包括包括多个存储器单元块的存储器阵列。 该装置还包括执行泄漏抑制处理的控制器。 泄漏抑制过程包括确定给定的存储单元块包括一个或多个过擦除存储器单元。 在确定时，泄漏抑制处理还包括执行软程序操作以增加给定块中的被擦除的存储器单元的阈值电压。