公开(公告)号：US06665216B1

公开(公告)日：2003-12-16

申请号：US10202245

申请日：2002-07-23

申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

IPC分类号： G11C700

CPC分类号： G11C16/28 ,  G11C7/062

摘要： A system for reading data in a memory cell includes three comparators, each of which has two inputs. A first reference cell having a low reference voltage is coupled to one input of the first comparator. A second reference cell having a high reference voltage is coupled to one input of the second comparator. A memory cell having a memory cell voltage is coupled to the other input of the first and second comparators. One input of the third comparator is coupled to the first comparator's output signal, which includes a difference voltage between the memory cell voltage and the low reference voltage. The other input of the third comparator is coupled to the second comparator's output signal, which includes a difference voltage between the memory cell voltage and the high reference voltage. A method and apparatus for reading data in a memory cell also are described.

摘要翻译： 用于读取存储器单元中的数据的系统包括三个比较器，每个比较器具有两个输入。 具有低参考电压的第一参考单元耦合到第一比较器的一个输入端。 具有高参考电压的第二参考单元耦合到第二比较器的一个输入端。 具有存储单元电压的存储单元耦合到第一和第二比较器的另一个输入端。 第三比较器的一个输入耦合到第一比较器的输出信号，其包括存储单元电压和低参考电压之间的差电压。 第三比较器的另一输入端耦合到第二比较器的输出信号，其包括存储单元电压和高参考电压之间的差电压。 还描述了一种用于在存储器单元中读取数据的方法和装置。

公开(公告)号：US06845052B1

公开(公告)日：2005-01-18

申请号：US10250040

申请日：2003-05-30

申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

IPC分类号： G11C7/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C16/28 ,  G11C2207/2227

摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.

摘要翻译： 本发明提供了一种用于非易失性存储器的双参考单元感测方案。 高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。 两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。 双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。 双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

公开(公告)号：US06421267B1

公开(公告)日：2002-07-16

申请号：US09840709

申请日：2001-04-24

申请人： Nai-Ping Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

发明人： Nai-Ping Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

IPC分类号： G11C1134

CPC分类号： G11C16/3495 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/16

摘要： A memory array architecture includes a plurality of memory cells formed into rows and columns. A plurality of bit lines is connected to the memory cells through select transistors. By disposing adjacent bit lines into different metal layers or alternatively interlocating adjacent bit lines, the coupling effect between bit lines can be effectively reduced, and thus can improve reading speed of memory while performing read operation.

摘要翻译： 存储器阵列结构包括形成行和列的多个存储单元。 多个位线通过选择晶体管连接到存储单元。 通过将相邻的位线布置在不同的金属层中或者可选地相互位置相邻的位线，可以有效地减少位线之间的耦合效应，从而可以在执行读取操作时提高存储器的读取速度。

公开(公告)号：US06563735B1

公开(公告)日：2003-05-13

申请号：US10117148

申请日：2002-04-04

申请人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

发明人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

IPC分类号： G11C1604

CPC分类号： G11C16/0491

摘要： A NOR-structured semiconductor memory device with a novel configuration of bit line connection is disclosed. The NOR-structured semiconductor memory device comprises a semiconductor memory cell array electrically connected to a plurality of bit lines. The plurality of bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main bit line through at least two bit line transistors, respectively. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively. During a programming or data reading operation, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage or sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device successfully prevents the programming disturbance or correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.

摘要翻译： 公开了具有位线连接的新颖结构的NOR结构的半导体存储器件。 NOR结构的半导体存储器件包括电连接到多个位线的半导体存储单元阵列。 多个位线被分成至少四个位线组。 每个位线组的至少两个位线分别通过至少两个位线晶体管耦合到主位线。 此外，NOR结构半导体存储器件的位线被布置成使得其中至少四个相邻的位线分别从四个不同的位线组中选择并且分别耦合到四个不同的主位线。 在编程或数据读取操作期间，四个相邻位线中的两个相邻位线被提供有编程电压或感测电流，而另外两个相邻位线接地。 因此，由于没有形成泄漏电流路径，所以NOR结构的半导体存储器件成功地防止了编程干扰或者以高速正确地确定存储在存储单元中的数据。

公开(公告)号：US20090021994A1

公开(公告)日：2009-01-22

申请号：US11779951

申请日：2007-07-19

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.

摘要翻译： 一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。 首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。 接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

公开(公告)号：US07649772B2

公开(公告)日：2010-01-19

申请号：US11779951

申请日：2007-07-19

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho ,  Wen-Chiao Ho

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.

摘要翻译： 一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。 首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。 接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

公开(公告)号：US20110085378A1

公开(公告)日：2011-04-14

申请号：US12576323

申请日：2009-10-09

申请人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

发明人： Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Yun-Chen Chou

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/349

摘要： In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.

摘要翻译： 在包括多个存储单元的存储器的操作方法中，通过施加参考电压对存储器单元执行第一读取; 如果检查到第一读取结果不正确，则移动参考电压; 通过施加移动的参考电压对存储器单元执行第二读取; 如果检查到第二读取结果不正确，则将第一读取中的第一逻辑状态的第一总数与第二读取中的第一逻辑状态的第二总数进行比较; 并且如果第一读取结果具有与第二读取结果相同数量的第一逻辑状态，并且移动的参考电压被存储为目标参考电压，则参考电压的移动停止。

公开(公告)号：US20110055670A1

公开(公告)日：2011-03-03

申请号：US12943443

申请日：2010-11-10

申请人： Chun-Hsiung Hung ,  Hsin-Yi Ho

发明人： Chun-Hsiung Hung ,  Hsin-Yi Ho

IPC分类号： G11C11/40 ,  G11C7/00 ,  G06F11/07

CPC分类号： G11C16/3404 ,  G11C16/3454

摘要： A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.

摘要翻译： 提供了一种应用于存储器的编程方法。 存储器包括多个存储单元。 该方法包括以下步骤。 响应于第一编程命令对存储器单元的目标单元进行编程。 响应于第二编程命令对目标单元进行编程。

公开(公告)号：US20120265923A1

公开(公告)日：2012-10-18

申请号：US13086988

申请日：2011-04-14

申请人： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen

发明人： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F11/00 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C16/10 ,  G11C16/105 ,  G11C2211/5648

摘要： A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.

摘要翻译： 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。

公开(公告)号：US20110069544A1

公开(公告)日：2011-03-24

申请号：US12566144

申请日：2009-09-24

申请人： Hsin-Yi Ho ,  Chia-Ching Li ,  Chun-Hsiung Hung

发明人： Hsin-Yi Ho ,  Chia-Ching Li ,  Chun-Hsiung Hung

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program phase, and verifying the first memory cell with a first post program-verify voltage of the first program phase (PV1′) in which the first post program-verify voltage is different from the first preliminary voltage. A corresponding apparatus is also provided.

摘要翻译： 编程包括多个存储器单元的存储器件的方法可以包括使用第一编程相位（PPV1'）的第一初级电压来验证目标为第一电平的第一存储器单元，编程针对第一级的第一存储器单元 在第一编程阶段中，并且以第一编程后验证电压与第一初步电压不同的第一编程相位（PV1'）的第一后编程验证电压来验证第一存储单元。 还提供了相应的装置。