公开(公告)号：US20050147926A1

公开(公告)日：2005-07-07

申请号：US10749590

申请日：2004-01-02

申请人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ta Wang

发明人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ta Wang

IPC分类号： G03F7/00 ,  G03F7/16 ,  G03F7/36 ,  G03F7/40

CPC分类号： G03F7/168 ,  G03F7/40 ,  G03F7/405

摘要： Disclosed is a method for processing photoresist. The method of the present invention performs Ar plasma process to the photoresist after or before the photoreisist is formed into a pattern to make the photoresist dense.

摘要翻译： 公开了一种处理光致抗蚀剂的方法。 本发明的方法在光电导体形成图案之后或之后对光致抗蚀剂进行Ar等离子体处理以使光致抗蚀剂致密。

公开(公告)号：US20050118531A1

公开(公告)日：2005-06-02

申请号：US10707259

申请日：2003-12-02

申请人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： G03F7/00 ,  G03F7/36 ,  H01L21/027 ,  H01L21/3213

CPC分类号： H01L21/0274 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for controlling line width critical dimension is disclosed. A semiconductor layer is deposited on a substrate. A cap layer is formed on the semiconductor layer. A patterned photoresist is formed on the cap layer. The patterned photoresist has a top surface and vertical sidewalls. A silicon thin film is selectively sputtered on the top surface and vertical sidewalls of the patterned photoresist, but not on the cap layer. The silicon thin film, which has a thickness: x above the top surface and a thickness: y on the sidewalls of the patterned photoresist, wherein xx

摘要翻译： 公开了一种用于控制线宽临界尺寸的方法。 在衬底上沉积半导体层。 在半导体层上形成覆盖层。 在盖层上形成图案化的光致抗蚀剂。 图案化的光致抗蚀剂具有顶表面和垂直侧壁。 硅薄膜在图案化光致抗蚀剂的顶表面和垂直侧壁上被选择性溅射，但不在盖层上。 硅薄膜的厚度x高于顶表面，图案化光致抗蚀剂的侧壁上的厚度为：y，其中xx <，用于保护图案化的光致抗蚀剂。 使用硅薄膜和图案化的光致抗蚀剂作为蚀刻掩模，封盖层被各向异性蚀刻，从而将光刻胶图案转印到盖层。 最后，使用盖层作为蚀刻掩模，蚀刻半导体层。

公开(公告)号：US06974741B2

公开(公告)日：2005-12-13

申请号：US10751503

申请日：2004-01-06

申请人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/3081 ,  H01L21/3086 ,  H01L21/76224

摘要： Disclosed is a method for forming a shallow trench. The method of the present invention comprises steps of providing a substrate; forming a plurality of operation layers on the substrate; forming photoresist on the uppermost one of the operation layers to define a position to be etched; etching a portion of the operation layers at said position to form an opening; forming a spacing layer on the sidewall of the opening; and etching a portion of the substrate corresponding to the opening to form a shallow trench. By the etching method of the present invention, a striation phenomenon caused by the common mask etch is avoided.

公开(公告)号：US20050148152A1

公开(公告)日：2005-07-07

申请号：US10751503

申请日：2004-01-06

申请人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76 ,  H01L21/311

CPC分类号： H01L21/3081 ,  H01L21/3086 ,  H01L21/76224

摘要： Disclosed is a method for forming a shallow trench. The method of the present invention comprises steps of providing a substrate; forming a plurality of operation layers on the substrate; forming photoresist on the uppermost one of the operation layers to define a position to be etched; etching a portion of the operation layers at said position to form an opening; forming a spacing layer on the sidewall of the opening; and etching a portion of the substrate corresponding to the opening to form a shallow trench. By the etching method of the present invention, a striation phenomenon caused by the common mask etch is avoided.

摘要翻译： 公开了一种形成浅沟槽的方法。 本发明的方法包括提供基底的步骤; 在所述基板上形成多个操作层; 在最上面的操作层上形成光致抗蚀剂以限定待蚀刻的位置; 在所述位置蚀刻操作层的一部分以形成开口; 在所述开口的侧壁上形成间隔层; 并且蚀刻对应于所述开口的所述基板的一部分以形成浅沟槽。 通过本发明的蚀刻方法，避免了由普通掩模蚀刻引起的条纹现象。

公开(公告)号：US08963282B2

公开(公告)日：2015-02-24

申请号：US13231961

申请日：2011-09-14

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/72 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

摘要翻译： 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08692245B2

公开(公告)日：2014-04-08

申请号：US13214227

申请日：2011-08-21

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/544 ,  H01L23/482 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

摘要翻译： 本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US20130062727A1

公开(公告)日：2013-03-14

申请号：US13231961

申请日：2011-09-14

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

摘要翻译： 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US06992393B2

公开(公告)日：2006-01-31

申请号：US10708848

申请日：2004-03-29

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

摘要翻译： 提供一种用于制造互连的方法。 该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。 由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。

公开(公告)号：US06964926B2

公开(公告)日：2005-11-15

申请号：US10727924

申请日：2003-12-04

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/20 ,  H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  Y10S438/942

摘要： A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.

摘要翻译： 一种形成具有几何深沟槽的电容器的方法。 首先，提供在其上形成有衬垫结构的衬底，并且在衬垫结构上形成第一硬掩模层。 接着，在第一硬掩模层上形成第二硬掩模层。 接下来，在第一硬掩模层上的第一开口中形成间隔层以露出第二开口。 接下来，在第二开口填充第三硬掩模层，并且移除间隔层。 接下来，第一硬掩模层被蚀刻以暴露具有第一硬掩模层的凸起的第三开口，第二硬掩模层和第三硬掩模层用作掩模。 最后，蚀刻第一硬掩模层，焊盘结构和衬底以形成几何深沟槽。

公开(公告)号：US06908840B2

公开(公告)日：2005-06-21

申请号：US10640096

申请日：2003-08-13

申请人： Tse-Yao Huang ,  Yi-Nan Chen

发明人： Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76847 ,  H01L27/10873 ,  H01L27/10888

摘要： A method of filling a bit line contact via. The method includes providing a substrate having a transistor, with a gate electrode, drain region, and source region, on the substrate, forming a first barrier layer overlying the sidewall of the gate electrode, drain region, and source region, forming a first conductive layer overlying the first barrier layer, removing the first barrier layer and first conductive layer above the source region, forming an insulating barrier layer overlying the substrate, forming a first dielectric layer overlying the insulating barrier layer above the source region, forming a second dielectric layer overlying the substrate, forming a via through the second dielectric layer and the insulative barrier layer, exposing the first conductive layer, forming a second barrier layer overlying the surface of the via, and filling the via with a second conductive layer.

摘要翻译： 填充位线接触通孔的方法。 该方法包括在衬底上提供具有栅电极，漏极区和源极区的晶体管的衬底，形成覆盖在栅电极，漏区和源极区的侧壁上的第一势垒层，形成第一导电 层，覆盖第一阻挡层，去除源极区上方的第一阻挡层和第一导电层，形成覆盖在衬底上的绝缘阻挡层，形成覆盖在源区上方的绝缘阻挡层的第一介电层，形成第二介电层 覆盖衬底，通过第二电介质层和绝缘阻挡层形成通孔，暴露第一导电层，形成覆盖通孔表面的第二阻挡层，并用第二导电层填充通孔。