ALL DIGITAL PHASE LOCK LOOP AND METHOD FOR CONTROLLING PHASE LOCK LOOP
    1.
    发明申请
    ALL DIGITAL PHASE LOCK LOOP AND METHOD FOR CONTROLLING PHASE LOCK LOOP 有权
    所有数字相位锁定和控制相位锁定的方法

    公开(公告)号:US20090153255A1

    公开(公告)日:2009-06-18

    申请号:US12330100

    申请日:2008-12-08

    CPC classification number: H03L7/107 H03L7/0991 H03L7/10 H03L7/1806 H03L2207/50

    Abstract: An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word.

    Abstract translation: 公开了一种全数字锁相环,包括数字控制振荡器,相位检测器和环路滤波器。 数字控制振荡器由振荡器调谐字控制,以产生可变信号。 振荡器调谐字包括第一调谐字和第二调谐字,其中能够由第二调谐字调节的数字控制振荡器的频率范围比能够被第一调谐字调整的频率范围宽。 相位检测器检测可变信号和参考信号之间的相位误差。 相位误差由环路滤波器接收以输出振荡器调谐字。 环路滤波器具有几级低通滤波器和修改电路。 修改电路检测滤波器中的两个低通滤波器的两个滤波器输​​出,并相应地调整第二个调谐字。

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