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公开(公告)号：US08564319B2
公开(公告)日：2013-10-22
申请号：US12817735
申请日：2010-06-17
Applicant: You-Hua Chou , Yi-Jen Lai
Inventor： You-Hua Chou , Yi-Jen Lai
CPC classification number: G01R1/07307 , G01R1/07314 , G01R3/00
Abstract: In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure.
Abstract translation: 根据一个实施例，探针卡包括接触垫接口，其包括电连接在一起的前侧触点和后侧触点。 前侧触点被布置成同时电耦合在晶片上的多个管芯的相应凸起，并且后侧触点被布置成电耦合测试结构的各个触点。
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公开(公告)号：US08941232B2
公开(公告)日：2015-01-27
申请号：US13034263
申请日：2011-02-24
Applicant: You-Hua Chou , Yi-Jen Lai , Chun-Jen Chen , Perre Kao
Inventor： You-Hua Chou , Yi-Jen Lai , Chun-Jen Chen , Perre Kao
IPC: H01L23/34 , H01L23/367 , H01L23/42
CPC classification number: H01L23/473 , H01L23/3677 , H01L23/42 , H01L23/48 , H01L23/488 , H01L24/11 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L2224/11849 , H01L2224/16145 , H01L2924/01029 , H01L2924/014 , H01L2924/15 , H01L2924/15311 , H01L2924/351 , H01L2924/00
Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.
Abstract translation: 用于形成连接到本文所述的冷却装置（或散热器）的金属凸块的机构使得具有装置的基板能够更有效地散发产生的热量。 此外，金属凸块允许定制凹凸设计以满足不同芯片的需要。 此外，半导体芯片和冷却装置之间的金属凸块的使用能够通过在凸块之间传递冷却流体而进行先进的冷却。
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公开(公告)号：US08541262B2
公开(公告)日：2013-09-24
申请号：US12874816
申请日：2010-09-02
Applicant: Yi-Jen Lai , You-Hua Chou , Hon-Lin Huang , Huai-Tei Yang
Inventor： Yi-Jen Lai , You-Hua Chou , Hon-Lin Huang , Huai-Tei Yang
IPC: H01L23/50
CPC classification number: H01L23/481 , H01L21/76898 , H01L24/03 , H01L24/05 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/03823 , H01L2224/03825 , H01L2224/0401 , H01L2224/05006 , H01L2224/05009 , H01L2224/05147 , H01L2224/05568 , H01L2224/0557 , H01L2224/05655 , H01L2225/06541 , H01L2225/06551 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1434 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/01046 , H01L2924/00 , H01L2224/05552
Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.
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公开(公告)号：US20120217628A1
公开(公告)日：2012-08-30
申请号：US13034263
申请日：2011-02-24
Applicant: You-Hua CHOU , Yi-Jen LAI , Chun-Jen CHEN , Perre KAO
Inventor： You-Hua CHOU , Yi-Jen LAI , Chun-Jen CHEN , Perre KAO
CPC classification number: H01L23/473 , H01L23/3677 , H01L23/42 , H01L23/48 , H01L23/488 , H01L24/11 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L2224/11849 , H01L2224/16145 , H01L2924/01029 , H01L2924/014 , H01L2924/15 , H01L2924/15311 , H01L2924/351 , H01L2924/00
Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.
Abstract translation: 用于形成连接到本文所述的冷却装置（或散热器）的金属凸块的机构使得具有装置的基板能够更有效地散发产生的热量。 此外，金属凸块允许定制凹凸设计以满足不同芯片的需要。 此外，半导体芯片和冷却装置之间的金属凸块的使用能够通过在凸块之间传递冷却流体而进行先进的冷却。
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公开(公告)号：US08610270B2
公开(公告)日：2013-12-17
申请号：US12702636
申请日：2010-02-09
Applicant: Yi-Jen Lai , Chih-Kang Han , Chien-Pin Chan , Chih-Yuan Chien , Huai-Tei Yang
Inventor： Yi-Jen Lai , Chih-Kang Han , Chien-Pin Chan , Chih-Yuan Chien , Huai-Tei Yang
IPC: H01L23/498 , H01L23/48
CPC classification number: H01L24/13 , H01L21/6836 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1357 , H01L2224/136 , H01L2224/16 , H01L2224/16237 , H01L2224/81001 , H01L2224/812 , H01L2224/81815 , H01L2224/97 , H01L2225/06513 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2924/351 , H01L2924/3651 , H01L2224/81 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.
Abstract translation: 半导体器件包括在焊盘区域上的凸块结构。 凸块结构包括在铜层上的铜层和无铅焊料层。 无铅焊料层是SnAg层，SnAg层中的Ag含量小于1.6重量％。
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Patent Agency Ranking
公开(公告)号：US20130026623A1
公开(公告)日：2013-01-31
申请号：US13194606
申请日：2011-07-29
Applicant: Yu-Ren Chen , Ming Hung Tseng , Yi-Jen Lai
Inventor： Yu-Ren Chen , Ming Hung Tseng , Yi-Jen Lai
IPC: H01L23/485 , H01L21/56
CPC classification number: H01L23/562 , H01L21/563 , H01L23/16 , H01L23/3128 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L2224/0401 , H01L2224/05569 , H01L2224/05572 , H01L2224/06155 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13647 , H01L2224/13655 , H01L2224/16225 , H01L2224/73103 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/92125 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/014 , H01L2224/05552 , H01L2924/00 , H01L2924/00012
Abstract: Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.
Abstract translation: 公开了半导体器件，封装方法和结构。 在一个实施例中，半导体器件包括具有周边区域和中心区域的表面的集成电路管芯。 在周边区域中的集成电路管芯的表面上设置有多个突起。 间隔件设置在中心区域的集成电路管芯的表面上。
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公开(公告)号：US20120056328A1
公开(公告)日：2012-03-08
申请号：US12874816
申请日：2010-09-02
Applicant: Yi-Jen Lai , You-Hua Chou , Hon-Lin Huang , Huai-Tei Yang
Inventor： Yi-Jen Lai , You-Hua Chou , Hon-Lin Huang , Huai-Tei Yang
CPC classification number: H01L23/481 , H01L21/76898 , H01L24/03 , H01L24/05 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/03823 , H01L2224/03825 , H01L2224/0401 , H01L2224/05006 , H01L2224/05009 , H01L2224/05147 , H01L2224/05568 , H01L2224/0557 , H01L2224/05655 , H01L2225/06541 , H01L2225/06551 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1434 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/01046 , H01L2924/00 , H01L2224/05552
Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.
Abstract translation: 提供了利用芯片边缘触点的半导体器件。 集成电路管芯具有后钝化层，其具有填充有从接触件延伸到管芯边缘的导电材料的沟槽，从而形成管芯边缘接触。 可选地，贯穿衬底通孔可以沿着管芯边缘定位，使得沟槽中的导电材料电连接到贯穿衬底通孔，从而形成更大的管芯边缘接触。 集成电路管芯可以放置在多管芯封装中，其中多管芯封装包括具有垂直于集成电路管芯的主表面的主表面的壁。 模边缘触点电耦合到多模封装的壁上的触点。 多管芯封装可以包括用于连接到另一衬底的边缘触点，例如印刷电路板，封装衬底，高密度互连等。
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公开(公告)号：US20110309854A1
公开(公告)日：2011-12-22
申请号：US12817735
申请日：2010-06-17
Applicant: You-Hua Chou , Yi-Jen Lai
Inventor： You-Hua Chou , Yi-Jen Lai
IPC: G01R31/02
CPC classification number: G01R1/07307 , G01R1/07314 , G01R3/00
Abstract: In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure.
Abstract translation: 根据一个实施例，探针卡包括接触垫接口，其包括电连接在一起的前侧触点和后侧触点。 前侧触点被布置成同时电耦合在晶片上的多个管芯的相应凸起，并且后侧触点被布置成电耦合测试结构的各个触点。
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公开(公告)号：US20110193219A1
公开(公告)日：2011-08-11
申请号：US12702636
申请日：2010-02-09
Applicant: Yi-Jen LAI , Chih-Kang Han , Chien-Pin Chan , Chih-Yuan Chien , Huai-Tei Yang
Inventor： Yi-Jen LAI , Chih-Kang Han , Chien-Pin Chan , Chih-Yuan Chien , Huai-Tei Yang
IPC: H01L23/498 , H01L21/60
CPC classification number: H01L24/13 , H01L21/6836 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1357 , H01L2224/136 , H01L2224/16 , H01L2224/16237 , H01L2224/81001 , H01L2224/812 , H01L2224/81815 , H01L2224/97 , H01L2225/06513 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2924/351 , H01L2924/3651 , H01L2224/81 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.
Abstract translation: 半导体器件包括在焊盘区域上的凸块结构。 凸块结构包括在铜层上的铜层和无铅焊料层。 无铅焊料层是SnAg层，SnAg层中的Ag含量小于1.6重量％。
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公开(公告)号：US08916969B2
公开(公告)日：2014-12-23
申请号：US13194606
申请日：2011-07-29
Applicant: Yu-Ren Chen , Ming Hung Tseng , Yi-Jen Lai
Inventor： Yu-Ren Chen , Ming Hung Tseng , Yi-Jen Lai
CPC classification number: H01L23/562 , H01L21/563 , H01L23/16 , H01L23/3128 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L2224/0401 , H01L2224/05569 , H01L2224/05572 , H01L2224/06155 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13647 , H01L2224/13655 , H01L2224/16225 , H01L2224/73103 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/92125 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/014 , H01L2224/05552 , H01L2924/00 , H01L2924/00012
Abstract: Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.
Abstract translation: 公开了半导体器件，封装方法和结构。 在一个实施例中，半导体器件包括具有周边区域和中心区域的表面的集成电路管芯。 在周边区域中的集成电路管芯的表面上设置有多个突起。 间隔件设置在中心区域的集成电路管芯的表面上。
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