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    Data storage method and phase change memory
    2.
    发明授权
    Data storage method and phase change memory 有权

    公开(公告)号：US09899084B2

    公开(公告)日：2018-02-20

    申请号：US15412509

    申请日：2017-01-23

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Shujie Zhang

    IPC: G11C11/56 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/79

    Abstract: A data storage method applying to the phase change memory and a phase change memory are provided. After obtaining to-be-stored data, the phase change memory generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal is a signal including at least two consecutive pulses with a same amplitude. The amplitude of the at least two consecutive pulses is a value determined according to the to-be-stored data. Then, the phase change memory applies the erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state. Further, the write pulse signal is applied to the storage unit to allow the storage unit to switch to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

    Hamming weight calculation method based on operation apparatus
    3.
    发明授权
    Hamming weight calculation method based on operation apparatus 有权

    公开(公告)号：US11817880B2

    公开(公告)日：2023-11-14

    申请号：US17895466

    申请日：2022-08-25

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Yi Li ,  Jiancong Li ,  Xiangshui Miao ,  Peng Yan ,  Guiyou Pu ,  Xiaozhong Shi ,  Keji Huang

    IPC: H03M13/19 ,  H03M13/00

    CPC classification number: H03M13/19 ,  H03M13/611

    Abstract: The present application discloses a Hamming weight calculation method performed by an operation apparatus. The operation apparatus includes a controller and a first calculator, wherein the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in a first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.

    Data storage method and phase change memory
    4.
    发明授权
    Data storage method and phase change memory 有权

    公开(公告)号：US10083749B2

    公开(公告)日：2018-09-25

    申请号：US15412795

    申请日：2017-01-23

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

    IPC: G11C11/56 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C11/5678 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0092

    Abstract: A data storage method applying to a phase change memory and the phase change memory are provided. After obtaining to-be-stored data, the phase change memory (PCM) generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal includes at least two contiguous pulses. Intervals between the at least two contiguous pulses are the same. The intervals between the at least two contiguous pulses have a value determined according to the to-be-stored data. The PCM applies the erase pulse signal to a storage unit of the PCM to enable the storage unit to change to a crystalline state. Further, the write pulse signal is applied to the storage unit to enable the storage unit to change to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

    Data Storage Method and Phase Change Memory
    6.
    发明申请
    Data Storage Method and Phase Change Memory 审中-公开

    公开(公告)号：US20170133090A1

    公开(公告)日：2017-05-11

    申请号：US15412795

    申请日：2017-01-23

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C11/5678 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0092

    Abstract: A data storage method applying to a phase change memory and the phase change memory are provided. After obtaining to-be-stored data, the phase change memory (PCM) generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal includes at least two contiguous pulses. Intervals between the at least two contiguous pulses are the same. The intervals between the at least two contiguous pulses have a value determined according to the to-be-stored data. The PCM applies the erase pulse signal to a storage unit of the PCM to enable the storage unit to change to a crystalline state. Further, the write pulse signal is applied to the storage unit to enable the storage unit to change to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

    Data Storage Method and Phase Change Memory
    7.
    发明申请
    Data Storage Method and Phase Change Memory 有权

    公开(公告)号：US20170133089A1

    公开(公告)日：2017-05-11

    申请号：US15412509

    申请日：2017-01-23

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Shujie Zhang

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/79

    Abstract: A data storage method applying to the phase change memory and a phase change memory are provided. After obtaining to-be-stored data, the phase change memory generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal is a signal including at least two consecutive pulses with a same amplitude. The amplitude of the at least two consecutive pulses is a value determined according to the to-be-stored data. Then, the phase change memory applies the erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state. Further, the write pulse signal is applied to the storage unit to allow the storage unit to switch to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

    Latch and D Flip-Flop
    8.
    发明申请
    Latch and D Flip-Flop 审中-公开
    锁扣和D触发器

    公开(公告)号：US20170040982A1

    公开(公告)日：2017-02-09

    申请号：US15331209

    申请日：2016-10-21

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Xiangshui Miao ,  Yi Li ,  Yaxiong Zhou ,  Ronggang Xu ,  Junfeng Zhao ,  Shujie Zhang

    IPC: H03K3/3562 ,  G11C13/00

    CPC classification number: H03K3/35625 ,  G11C13/0002 ,  H03K3/0372

    Abstract: A latch and a D flip-flop, where the latch includes a switch, a resistive random-access memory, a bleeder circuit, and a voltage converter. The voltage converter is configured to output an output signal of the latch according to an input signal of the latch when the switch is in an on state, where the output signal remains consistent with the input signal. When the switch changes from the on state to an off state, the resistive random-access memory is configured to work together with the bleeder circuit to enable an output signal of the latch when the switch is in the off state to remain consistent with an output signal of the latch when the switch is in the on state, thereby implementing a nonvolatile latching function. A circuit structure of the latch is simple and integrity of an existing logic circuit can be improved.

    Abstract translation: 锁存器和D触发器，其中锁存器包括开关，电阻随机存取存储器，泄放电路和电压转换器。 电压转换器被配置为当开关处于导通状态时根据锁存器的输入信号输出锁存器的输出信号，其中输出信号与输入信号保持一致。 当开关从导通状态变为断开状态时，电阻随机存取存储器被配置为与泄放电路一起工作，以便当开关处于断开状态时使锁存器的输出信号保持与输出一致 当开关处于导通状态时锁存器的信号，从而实现非易失性锁存功能。 锁存器的电路结构简单，可以提高现有逻辑电路的完整性。

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