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公开(公告)号：US07279753B1
公开(公告)日：2007-10-09
申请号：US11015402
申请日：2004-12-17
CPC分类号： H01L29/735 , H01L27/0259 , H01L29/1008
摘要： The present invention includes a bipolar ESD device for protecting an integrated circuit from ESD damage. The bipolar ESD device includes a collector connected to a terminal of the integrated circuit, a floating base, and a grounded emitter. When an ESD pulse hits the terminal of the integrated circuit, the PN junction between the emitter and the base becomes forward biased. The forward biasing of the emitter-base PN junction in turn causes carriers to be injected into the collector-base junction, triggering the bipolar ESD device to turn on to discharge the ESD pulse. The trigger voltage of the bipolar ESD device is a fraction of a breakdown voltage of the collector-base PN junction and can be modified by adjusting a base length of the bipolar ESD device, a junction depth of the collector, or a dopant concentration in the base.
摘要翻译： 本发明包括用于保护集成电路免受ESD损坏的双极性ESD器件。 双极ESD器件包括连接到集成电路的端子的集电极，浮置基极和接地发射极。 当ESD脉冲击中集成电路的端子时，发射极和基极之间的PN结变为正向偏置。 发射极 - 基极PN结的正向偏置又会使载流子注入到集电极 - 基极结中，触发双极型ESD器件导通以释放ESD脉冲。 双极ESD器件的触发电压是集电极 - 基极PN结的击穿电压的一小部分，可以通过调整双极ESD器件的基极长度，集电极的结深度或者掺杂剂浓度 基础。
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公开(公告)号：US07471493B1
公开(公告)日：2008-12-30
申请号：US11365070
申请日：2006-02-28
CPC分类号： H01L27/0262 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A pair of SCR devices connected in antiparallel between first and second nodes. Each SCR device comprises an NPN and a PNP bipolar transistor. Reverse-biased Zener diodes are used for triggering the NPN bipolar transistor in each SCR device when it breaks down in an ESD event. Advantageously, additional Zener diodes are provided for pre-charging the PNP transistor of each SCR device at the same time, thereby reducing the delay time for turning on the PNP bipolar transistor. In addition, the breakdown current of the Zener diodes is preferably maximized by reducing the P-well and N-well resistance of the SCRs. This is achieved by connecting external resistances between the base of each bipolar transistor and the node to which the emitter of the transistor is connected.
摘要翻译： 在第一和第二节点之间反并联连接的一对SCR设备。 每个SCR器件包括NPN和PNP双极晶体管。 反向偏置齐纳二极管用于在ESD事件中发生故障时触发每个SCR器件中的NPN双极晶体管。 有利地，提供了额外的齐纳二极管，用于同时为每个SCR器件的PNP晶体管预充电，从而减少了导通PNP双极晶体管的延迟时间。 此外，通过降低SCR的P阱和N阱电阻，优选使齐纳二极管的击穿电流最大化。 这是通过连接每个双极晶体管的基极与晶体管的发射极连接的节点之间的外部电阻来实现的。
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公开(公告)号：US07821050B1
公开(公告)日：2010-10-26
申请号：US11497017
申请日：2006-07-31
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/118 , G11C5/005 , G11C11/4125 , H01L27/11 , H01L27/1104 , H01L29/4983 , H01L29/66659 , Y10S257/903
摘要： A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.
摘要翻译： 制造在半导体衬底上的晶体管包括衬底中的源极和漏极; 基板上的栅极，栅极通过栅极电介质与基板绝缘; 覆盖栅极和栅极电介质的两侧的阻挡层; 覆盖阻挡层的高k材料的间隔物; 以及覆盖高k材料的间隔物的氮化物间隔物。 高k材料的间隔物显着增加了晶体管的节点电容，从而降低了晶体管的软错误率。
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公开(公告)号：US07408754B1
公开(公告)日：2008-08-05
申请号：US10992591
申请日：2004-11-18
申请人： Hugh Sung-Ki O , Chih-Ching Shih , Yow-Juang Bill Liu , Cheng-Hsiung Huang , Wei-Guang Wu , Billy Jow-Tai Kwong , Yu-Cheng Richard Gao
发明人： Hugh Sung-Ki O , Chih-Ching Shih , Yow-Juang Bill Liu , Cheng-Hsiung Huang , Wei-Guang Wu , Billy Jow-Tai Kwong , Yu-Cheng Richard Gao
IPC分类号： H02H3/20
CPC分类号： H01L27/0262
摘要： The present invention provides an ESD device for protecting thin oxide layers in transistors or capacitors in an integrated circuit. In one embodiment, the ESD device includes a silicon-controlled rectifier (SCR), the SCR including a PNP bipolar transistor and a NPN bipolar transistor. The ESD device further includes first and second trigger devices coupled to the SCR and configured to simultaneously turn on the PNP bipolar transistor and the NPN bipolar transistor in response to an ESD pulse on the ESD device. The base of the NPN bipolar transistor is floating to allow a first external resistor to be connected between the base and emitter of the NPN bipolar transistor. A second external resistor can be connected between the base and emitter of the PNP bipolar transistor.
摘要翻译： 本发明提供一种用于在集成电路中保护晶体管或电容器中的薄氧化物层的ESD装置。 在一个实施例中，ESD器件包括硅控整流器（SCR），SCR包括PNP双极晶体管和NPN双极晶体管。 ESD器件还包括耦合到SCR的第一和第二触发器件，并被配置为响应于ESD器件上的ESD脉冲同时导通PNP双极晶体管和NPN双极晶体管。 NPN双极晶体管的基极是浮置的，以允许第一外部电阻器连接在NPN双极晶体管的基极和发射极之间。 第二个外部电阻可以连接在PNP双极晶体管的基极和发射极之间。
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公开(公告)号：US06897543B1
公开(公告)日：2005-05-24
申请号：US10646013
申请日：2003-08-22
申请人： Cheng H. Huang , Yowjuang Liu , Chih-Ching Shih , Hugh Sung-Ki O
发明人： Cheng H. Huang , Yowjuang Liu , Chih-Ching Shih , Hugh Sung-Ki O
IPC分类号： G11C17/16 , H01L21/8246 , H01L23/525 , H01L27/112 , H01L27/12 , H01L29/00
CPC分类号： H01L27/11206 , G11C17/16 , H01L23/5252 , H01L27/112 , H01L27/1203 , H01L2924/0002 , Y10S438/983 , H01L2924/00
摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.
摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）反熔丝晶体管用作电可编程反熔丝。 在其未编程状态下，反熔丝晶体管截止并具有较高的电阻。 在编程期间，反熔丝晶体管导通，其熔化下面的硅并导致晶体管电阻的永久性降低。 感测电路监视反熔丝晶体管的电阻并相应地提供高或低输出信号。 反熔丝晶体管可以在编程期间通过在其衬底处相对于其源极升高电压而导通。 衬底可以通过电阻器接地。 可能通过使电流流过电阻器而使衬底偏置。 可以通过引起漏极 - 衬底结的雪崩击穿或通过产生连接到电阻器的外部齐纳二极管电路的齐纳击穿来使电流流过电阻器。
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公开(公告)号：US07272067B1
公开(公告)日：2007-09-18
申请号：US11060925
申请日：2005-02-18
申请人： Cheng H. Huang , Yowjuang Liu , Chih-Ching Shih , Hugh Sung-Ki O
发明人： Cheng H. Huang , Yowjuang Liu , Chih-Ching Shih , Hugh Sung-Ki O
IPC分类号： G11C17/18
CPC分类号： H01L27/11206 , G11C17/16 , H01L23/5252 , H01L27/112 , H01L27/1203 , H01L2924/0002 , Y10S438/983 , H01L2924/00
摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.
摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）反熔丝晶体管用作电可编程反熔丝。 在其未编程状态下，反熔丝晶体管截止并具有较高的电阻。 在编程期间，反熔丝晶体管导通，其熔化下面的硅并导致晶体管电阻的永久性降低。 感测电路监视反熔丝晶体管的电阻并相应地提供高或低输出信号。 反熔丝晶体管可以在编程期间通过在其衬底处相对于其源极升高电压而导通。 衬底可以通过电阻器接地。 可能通过使电流流过电阻器而使衬底偏置。 可以通过引起漏极 - 衬底结的雪崩击穿或通过产生连接到电阻器的外部齐纳二极管电路的齐纳击穿来使电流流过电阻器。
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公开(公告)号：US07157782B1
公开(公告)日：2007-01-02
申请号：US10780427
申请日：2004-02-17
申请人： Chih-Ching Shih , Cheng H. Huang , Hugh Sung-Ki O , Yow-Juang Liu
发明人： Chih-Ching Shih , Cheng H. Huang , Hugh Sung-Ki O , Yow-Juang Liu
IPC分类号： H01L29/00 , H01L29/04 , H01L29/10 , H01L31/036 , H01L23/58
CPC分类号： H01L29/78 , H01L27/0203 , H01L27/112 , H01L27/11206
摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.
摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）晶体管用作电可编程反熔丝。 反熔丝晶体管具有源极，漏极，栅极和衬底端子。 栅极具有相关的栅极氧化物。 在其未编程状态下，栅极氧化物是完整的，并且反熔丝具有相对较高的电阻。 在编程期间，栅极氧化物分解，因此在其编程状态下，反熔丝晶体管具有相对低的电阻。 可以通过将热载流子注入到漏极附近的器件的衬底中来编程反熔丝晶体管。 由于漏极处的热载流子比衬底上的热载流子多，所以栅极氧化物不对称地受到应力，从而提高了编程效率。 可以使用反馈来帮助反熔丝晶体管打开以注入热载体。
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公开(公告)号：US07772591B1
公开(公告)日：2010-08-10
申请号：US11595329
申请日：2006-11-10
IPC分类号： H01L31/036
CPC分类号： H01L29/78 , H01L27/0203 , H01L27/112 , H01L27/11206
摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.
摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）晶体管用作电可编程反熔丝。 反熔丝晶体管具有源极，漏极，栅极和衬底端子。 栅极具有相关的栅极氧化物。 在其未编程状态下，栅极氧化物是完整的，并且反熔丝具有相对较高的电阻。 在编程期间，栅极氧化物分解，因此在其编程状态下，反熔丝晶体管具有相对低的电阻。 可以通过将热载流子注入到漏极附近的器件的衬底中来编程反熔丝晶体管。 由于漏极处的热载流子比衬底上的热载流子多，所以栅极氧化物不对称地受到应力，从而提高了编程效率。 可以使用反馈来帮助反熔丝晶体管打开以注入热载体。
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公开(公告)号：US07981753B1
公开(公告)日：2011-07-19
申请号：US12683402
申请日：2010-01-06
IPC分类号： H01L21/331
CPC分类号： H01L27/0266 , H01L21/265 , H01L29/0692 , H01L29/41775 , H01L29/456 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.
摘要翻译： 提供了一种用于提供静电放电（ESD）保护的装置。 该器件包括其中形成有漏极，源极和栅极的半导体衬底。 漏极包含具有比漏极和源极的其余部分的电阻高的电阻的区域。 栅极区域与该较高电阻区域和源极接触。 在一个实施例中，为了提供更高的电阻，较高的电阻缺少硅化物。 包括形成用于提供ESD保护的装置的方法。
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公开(公告)号：US20070002507A1
公开(公告)日：2007-01-04
申请号：US11173254
申请日：2005-07-01
申请人： Hugh O , Chih-Ching Shih , Cheng-Hsiung Huang , Yow-Juang Liu
发明人： Hugh O , Chih-Ching Shih , Cheng-Hsiung Huang , Yow-Juang Liu
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.
摘要翻译： ESD器件发明包括形成在衬底中的第一和第二晶体管，每个具有源极，漏极和栅极，第一事务的源极和漏极连接在地和I / O引脚或输入之间， 第一晶体管连接到地，并且第二晶体管的源极和漏极连接在第一晶体管的衬底和I / O引脚或输入之间; 在地和I / O引脚或输入之间串联连接的第一和第二电容器; 以及至少第三晶体管，其连接在第一和第二电容器之间的接地和节点之间，第二晶体管的栅极也连接到该节点。
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