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    INTEGRATED CIRCUIT DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS WITH SHIELD LINES INTERPOSED BETWEEN BIT LINES AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS WITH SHIELD LINES INTERPOSED BETWEEN BIT LINES AND METHODS OF FABRICATING THE SAME 有权
    集成电路设备，包括垂直通道晶体管与位线之间插入的屏蔽线及其制造方法

    公开(公告)号：US20110303974A1

    公开(公告)日：2011-12-15

    申请号：US13155688

    申请日：2011-06-08

    申请人： Hui-jung Kim ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Hyun-woo Chung

    发明人： Hui-jung Kim ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Hyun-woo Chung

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7788 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/7827

    摘要： An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.

    摘要翻译： 集成电路装置包括沿着第一方向从基板突出的多个支柱。 每个支柱包括在其相对端的源极/漏极区域和在源极/漏极区域之间延伸的沟道区域。 多个导电位线在基本上垂直于第一方向的第二方向上在基板上邻近柱子延伸。 多个导电屏蔽线在第二方向上在基板上延伸，使得每个屏蔽线在相邻的位线之间延伸。 还讨论了相关的制造方法。

    Semiconductor Devices Including Vertical Channel Transistors And Methods Of Manufacturing The Same
    3.
    发明申请
    Semiconductor Devices Including Vertical Channel Transistors And Methods Of Manufacturing The Same 有权
    包括垂直通道晶体管的半导体器件及其制造方法

    公开(公告)号：US20120025300A1

    公开(公告)日：2012-02-02

    申请号：US13185961

    申请日：2011-07-19

    申请人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

    发明人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

    摘要： A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.

    摘要翻译： 一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。 多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。 构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。 一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中 第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案 在多个第二沟槽中。

    Semiconductor devices including vertical channel transistors and methods of manufacturing the same
    4.
    发明授权
    Semiconductor devices including vertical channel transistors and methods of manufacturing the same 有权
    包括垂直沟道晶体管的半导体器件及其制造方法

    公开(公告)号：US08766354B2

    公开(公告)日：2014-07-01

    申请号：US13185961

    申请日：2011-07-19

    申请人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

    发明人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

    IPC分类号： H01L29/66

    CPC分类号： H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

    摘要： A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.

    摘要翻译： 一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。 多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。 构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。 一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中 第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案 在多个第二沟槽中。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR
    7.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR 有权
    制造包括垂直通道晶体管的半导体器件的方法

    公开(公告)号：US20120094454A1

    公开(公告)日：2012-04-19

    申请号：US13240135

    申请日：2011-09-22

    申请人： Young-seung Cho ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

    发明人： Young-seung Cho ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

    IPC分类号： H01L21/336 ,  H01L21/302

    CPC分类号： H01L29/7827 ,  H01L27/0207 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/66666

    摘要： A method of fabricating a semiconductor device including a vertical channel transistor. The method may include: forming a plurality of first device isolation layers in a substrate as a pattern of lines having a first depth from an upper surface of a substrate, to define a plurality of active regions, forming a plurality of trenches having a second depth smaller than the first depth, etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth, forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches, and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches.

    摘要翻译： 一种制造包括垂直沟道晶体管的半导体器件的方法。 该方法可以包括：在衬底中形成多个第一器件隔离层作为具有从衬底的上表面的第一深度的线的图案，以限定多个有源区，形成具有第二深度的多个沟槽 小于第一深度，蚀刻在以预定间隔选择的多个沟槽中的一些下方的衬底的部分，以形成具有大于第二深度的第三深度的多个器件隔离沟槽，形成第二深度 在所述多个器件隔离沟槽的下部包括绝缘材料的器件隔离层，以及在所述多个沟槽的下部和所述多个器件隔离沟槽中形成掩埋位线。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130037882A1

    公开(公告)日：2013-02-14

    申请号：US13571805

    申请日：2012-08-10

    申请人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

    发明人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L29/4236

    摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.

    摘要翻译： 半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部 沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08492832B2

    公开(公告)日：2013-07-23

    申请号：US13571805

    申请日：2012-08-10

    申请人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

    发明人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L29/4236

    摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.

    摘要翻译： 半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部 沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

    Semiconductor device having vertical channel transistor and method of manufacturing the same
    10.
    发明授权
    Semiconductor device having vertical channel transistor and method of manufacturing the same 有权
    具有垂直沟道晶体管的半导体器件及其制造方法

    公开(公告)号：US08420485B2

    公开(公告)日：2013-04-16

    申请号：US13243174

    申请日：2011-09-23

    申请人： Young-seung Cho ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

    发明人： Young-seung Cho ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7827 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/66666

    摘要： A semiconductor device and method of manufacturing the same. The method includes: defining a first active area and a second active area on a substrate, the first and second active areas being in a line form, forming a first main trench and a second main trench on the substrate, forming a first sub-trench and a second sub-trench in bottoms of the first and second main trenches, respectively, forming a buried insulation layer filling the first and second sub-trenches, partially exposing the substrate at an area where the first active area crosses with the first sub-trench and an area where the second active area crosses with the second sub-trench and forming the first buried bit line and the second buried bit line on the buried insulation layer, and the first and second buried bit lines being extended in parallel to each other.

    摘要翻译： 一种半导体器件及其制造方法。 该方法包括：在衬底上限定第一有源区和第二有源区，第一和第二有源区为线形，在衬底上形成第一主沟槽和第二主沟槽，形成第一子沟槽 以及分别在所述第一和第二主沟槽的底部中的第二子沟槽，形成填充所述第一和第二子沟槽的掩埋绝缘层，在所述第一有源区域与所述第一子沟槽交叉的区域部分地暴露所述衬底， 沟槽和第二有源区域与第二子沟槽交叉的区域，并且在掩埋绝缘层上形成第一掩埋位线和第二掩埋位线，并且第一和第二掩埋位线彼此平行地延伸 。