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    Structure to use an etch resistant liner on transistor gate structure to achieve high device performance
    1.
    发明授权
    Structure to use an etch resistant liner on transistor gate structure to achieve high device performance 有权
    在晶体管栅极结构上使用耐蚀刻衬里的结构来实现高器件性能

    公开(公告)号：US07307323B2

    公开(公告)日：2007-12-11

    申请号：US11369409

    申请日：2006-03-07

    申请人： Hung Y. Ng ,  Haining S. Yang

    发明人： Hung Y. Ng ,  Haining S. Yang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0629 ,  H01L29/6656

    摘要： An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

    摘要翻译： 覆盖晶体管栅极叠层的侧壁并且沿晶体管栅极堆叠的基极的衬底的一部分覆盖的耐蚀刻衬里。 衬垫防止在栅极堆叠的侧壁上形成硅化物，这可能产生电短路，并且确定在晶体管栅极堆叠的基极处的衬底内的源极和漏极区域内的硅化物形成的位置。 衬套还覆盖阻止在电阻器栅极叠层内或邻近电阻器栅叠层形成硅化物的电阻器栅极堆叠。

    Structure and method of forming a transistor with asymmetric channel and source/drain regions
    3.
    发明授权
    Structure and method of forming a transistor with asymmetric channel and source/drain regions 有权
    形成具有不对称沟道和源极/漏极区的晶体管的结构和方法

    公开(公告)号：US08674444B2

    公开(公告)日：2014-03-18

    申请号：US13422297

    申请日：2012-03-16

    申请人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

    发明人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

    摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.

    摘要翻译： 半导体结构包括半导体衬底。 导电栅极邻接栅极绝缘体，用于控制沟道区的导通。 栅极绝缘体邻接沟道区域。 源极区域和漏极区域与导电栅极相关联。 源极区域包括第一材料，漏极区域包括第二材料。 导电栅极与第一和第二材料自对准。

    Carrier mobility enhanced channel devices and method of manufacture
    4.
    发明授权
    Carrier mobility enhanced channel devices and method of manufacture 有权
    载波移动增强信道设备和制造方法

    公开(公告)号：US08461625B2

    公开(公告)日：2013-06-11

    申请号：US13080352

    申请日：2011-04-05

    申请人： Kangguo Cheng ,  Haining S. Yang

    发明人： Kangguo Cheng ,  Haining S. Yang

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7845 ,  Y10S438/926

    摘要： An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

    摘要翻译： 提供了具有应力增强通道的集成电路，设计结构和制造集成电路的方法。 该方法包括在衬底上形成虚拟栅极结构并在虚拟栅极结构中形成沟槽。 该方法还包括用应变诱导材料填充沟槽的一部分并用栅极材料填充沟槽的剩余部分。

    STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS
    6.
    发明申请
    STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS 有权
    用不对称通道和源/漏区形成晶体管的结构和方法

    公开(公告)号：US20120235236A1

    公开(公告)日：2012-09-20

    申请号：US13422297

    申请日：2012-03-16

    申请人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

    发明人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

    摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.

    摘要翻译： 半导体结构包括半导体衬底。 导电栅极邻接栅极绝缘体，用于控制沟道区的导通。 栅极绝缘体邻接沟道区域。 源极区域和漏极区域与导电栅极相关联。 源极区域包括第一材料，漏极区域包括第二材料。 导电栅极与第一和第二材料自对准。

    Double patterning process for integrated circuit device manufacturing
    7.
    发明授权
    Double patterning process for integrated circuit device manufacturing 有权
    集成电路器件制造的双重图案化工艺

    公开(公告)号：US08232210B2

    公开(公告)日：2012-07-31

    申请号：US12562222

    申请日：2009-09-18

    申请人： Kangguo Cheng ,  Haining S. Yang

    发明人： Kangguo Cheng ,  Haining S. Yang

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/32139 ,  H01L21/76816

    摘要： A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.

    摘要翻译： 形成集成电路（IC）器件特征的方法包括：在待图案化的半导体器件层上形成初始基本平坦的硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层中的第一组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第一组半导体器件特征; 去除第一光致抗蚀剂层; 在所述基本上平坦的硬掩模层上形成第二光致抗蚀剂层; 在第二光致抗蚀剂层中图形化第二组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第二组半导体器件特征; 去除所述第二光致抗蚀剂层; 以及通过移除与所述第一和第二组半导体器件特征对应的部分来在所述硬掩模层内产生形貌。

    SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS
    9.
    发明申请
    SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS 有权
    栅极电极区域之间具有减少的距离的半导体晶体管

    公开(公告)号：US20120126339A1

    公开(公告)日：2012-05-24

    申请号：US13357757

    申请日：2012-01-25

    申请人： Robert C. Wong ,  Haining S. Yang

    发明人： Robert C. Wong ,  Haining S. Yang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  Y10S257/903

    摘要： A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.

    摘要翻译： 半导体结构。 半导体结构包括：半导体衬底，其包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面，并且还包括第一半导体本体区域和第二半导体本体区域; 分别在第一和第二半导体本体区域的顶部上的第一栅极电介质区域和第二栅极电介质区域; 在所述半导体衬底和所述第一栅极电介质区域的顶部上的第一栅极电极区域; 在所述半导体衬底和所述第二栅极电介质区域的顶部上的第二栅极电极区域; 以及与第一和第二栅电极区域直接物理接触的栅极分压区域。 栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

    SOI substrates and SOI devices, and methods for forming the same
    10.
    发明授权
    SOI substrates and SOI devices, and methods for forming the same 有权
    SOI衬底和SOI器件及其形成方法

    公开(公告)号：US08159031B2

    公开(公告)日：2012-04-17

    申请号：US12709873

    申请日：2010-02-22

    申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

    发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

    IPC分类号： H01L27/12

    CPC分类号： H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

    摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

    摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。