公开(公告)号：US06828198B2

公开(公告)日：2004-12-07

申请号：US10392120

申请日：2003-03-19

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/28123 ,  H01L21/32139

摘要： A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

公开(公告)号：US20050083075A1

公开(公告)日：2005-04-21

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US06885214B1

公开(公告)日：2005-04-26

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US09362384B2

公开(公告)日：2016-06-07

申请号：US14559542

申请日：2014-12-03

申请人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

公开(公告)号：US20120241870A1

公开(公告)日：2012-09-27

申请号：US13373225

申请日：2011-11-08

申请人： Chien-Ling Chan ,  Yuh-Chyuan Wang ,  Hung-Der Su

发明人： Chien-Ling Chan ,  Yuh-Chyuan Wang ,  Hung-Der Su

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/7322 ,  H01L27/0623 ,  H01L27/1052 ,  H01L29/66272

摘要： The present invention discloses a bipolar junction transistor (BJT) with surface protection and a manufacturing method thereof. The BJT includes: a first conductive type base, a second conductive type emitter, and a second conductive type collector, which are formed in a substrate, wherein the base is formed between and separates the emitter and the collector, and the base includes a base contact region functioning as an electrical contact node of the base; and a gate structure which is formed on the substrate between the base contact region and the second conductive type emitter.

摘要翻译： 本发明公开了一种具有表面保护的双极结型晶体管（BJT）及其制造方法。 BJT包括：形成在基板中的第一导电型基极，第二导电型发射极和第二导电型集电极，其中基极形成在发射极和集电极之间并分离，并且基极包括基极 接触区域用作基座的电接触节点; 以及栅极结构，其形成在所述基极接触区域和所述第二导电型发射极之间。

公开(公告)号：US20110220997A1

公开(公告)日：2011-09-15

申请号：US12720834

申请日：2010-03-10

申请人： Tsung-Yi Huang ,  Huan-Ping Chu ,  Ching-Yao Yang ,  Hung-Der Su

发明人： Tsung-Yi Huang ,  Huan-Ping Chu ,  Ching-Yao Yang ,  Hung-Der Su

IPC分类号： H01L29/78 ,  H01L21/8249

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/66681

摘要： The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.

摘要翻译： 本发明公开了一种具有增加的穿通电压的LDMOS器件及其制造方法。 LDMOS器件包括：衬底; 在基板中形成的第一导电类型的阱; 形成在衬底中的隔离区; 井中的第二导电类型的体区; 身体的一个来源; 井中排水 基板上的栅极结构; 以及在身体区域下面的第一导电型掺杂区域，用于增加穿通电压。

公开(公告)号：US07768033B2

公开(公告)日：2010-08-03

申请号：US12385720

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US07759695B2

公开(公告)日：2010-07-20

申请号：US12385717

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

摘要翻译： 单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。 由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。 单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。 还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

公开(公告)号：US07535032B2

公开(公告)日：2009-05-19

申请号：US11165028

申请日：2005-06-24

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

摘要翻译： 单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。 由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。 单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。 还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

公开(公告)号：US20080153239A1

公开(公告)日：2008-06-26

申请号：US11805979

申请日：2007-05-25

申请人： Hung-Der Su ,  Ching-Yao Yang ,  Chien-Ling Chan

发明人： Hung-Der Su ,  Ching-Yao Yang ,  Chien-Ling Chan

IPC分类号： H01L21/336 ,  G03F1/00

CPC分类号： H01L21/823475 ,  H01L21/26586 ,  H01L21/76895 ,  H01L21/823425

摘要： According to the present invention, a semiconductor process for butting contact comprises: providing a substrate on which are formed two adjacent transistor gates; implanting a full area between the two adjacent transistor gates by a tilt angle, to form a lightly doped region of a first conductivity type; forming a heavily doped region of the first conductivity type and a heavily doped region of a second conductivity type in the area between the two adjacent transistor gates, in which the heavily doped region of the second conductivity type overrides the lightly doped region of the first conductivity type, and divides the heavily doped region of the first conductivity type into two areas; depositing a dielectric layer; and forming a butting contact in the dielectric layer which concurrently contacts the two divided heavily doped regions of the first conductivity type.

摘要翻译： 根据本发明，用于对接接触的半导体工艺包括：提供在其上形成两个相邻晶体管栅极的衬底; 在两个相邻的晶体管栅极之间以倾斜角注入全部区域，以形成第一导电类型的轻掺杂区域; 在所述两个相邻晶体管栅极之间的区域中形成第一导电类型的重掺杂区域和第二导电类型的重掺杂区域，其中所述第二导电类型的重掺杂区域覆盖所述第一导电类型的轻掺杂区域 并且将第一导电类型的重掺杂区域划分为两个区域; 沉积介电层; 以及在同时接触第一导电类型的两个分开的重掺杂区域的电介质层中形成对接触点。