公开(公告)号：US07678655B2

公开(公告)日：2010-03-16

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US06828198B2

公开(公告)日：2004-12-07

申请号：US10392120

申请日：2003-03-19

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/28123 ,  H01L21/32139

摘要： A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

公开(公告)号：US06696356B2

公开(公告)日：2004-02-24

申请号：US10038847

申请日：2001-12-31

申请人： Li-Hsin Tseng ,  Hsiu-Mei Yu ,  Ta-Yang Lin ,  Fang-Chung Liu ,  Kai-Ming Ching ,  Tung-Heng Shie

发明人： Li-Hsin Tseng ,  Hsiu-Mei Yu ,  Ta-Yang Lin ,  Fang-Chung Liu ,  Kai-Ming Ching ,  Tung-Heng Shie

IPC分类号： H01L2144

CPC分类号： H01L24/05 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014

摘要： A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad. Thereafter the remaining portions of the photoresist layer are removed. The electrically conductive material is reflown to provide a bump on the semiconductor device.

摘要翻译： 在半导体晶片或倒装芯片等基板上形成凸块而不产生金属带残留物的方法。 该方法包括提供具有接触焊盘并具有上钝化层和形成在上钝化层中的开口的半导体器件的步骤，暴露接触焊盘的一部分。 在上钝化层和接触焊盘上沉积凸块下冶金。 光致抗蚀剂层沉积在凸块下的金属上。 光致抗蚀剂层是干膜光致抗蚀剂。 光致抗蚀剂层被图案化以在光致抗蚀剂层中提供直到下凸块冶金并且与接触垫对准的开口。 对光致抗蚀剂层施加额外的能量以提高光致抗蚀剂层对凸块下金属的粘合性。 将导电材料沉积在形成在光致抗蚀剂层中的开口中，并且覆盖凸块下方的金属并与接触焊盘对准。 此后，除去光致抗蚀剂层的其余部分。 导电材料被重熔以在半导体器件上提供凸块。

公开(公告)号：US20080026518A1

公开(公告)日：2008-01-31

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/8234

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US06926818B1

公开(公告)日：2005-08-09

申请号：US09961557

申请日：2001-09-24

申请人： Yih-Ann Lin ,  Tung-Heng Shie ,  Kai-Ming Ching ,  Sheng-Liang Pan ,  Kuo-Liang Lu

发明人： Yih-Ann Lin ,  Tung-Heng Shie ,  Kai-Ming Ching ,  Sheng-Liang Pan ,  Kuo-Liang Lu

IPC分类号： C25D5/02

CPC分类号： C25D5/022 ,  H01L2224/0401 ,  H01L2224/05557

摘要： A method of forming a bump structure through the use of an electroplating solution, comprising the following steps. A substrate having an overlying conductive structure is provided. A patterned dry film resist is formed over the conductive structure. The patterned dry film resist having a trench exposing a portion of conductive structure. The patterned dry film resist adhering to the conductive structure at an interface. The structure is treated with a treatment that increases the adherence of the patterned dry film resist to the conductive structure at the interface. A conductive plug is over the exposed portion of the conductive structure within the trench through the use of the electroplating solution. The increased adhesion of the patterned dry film resist to the conductive structure at the interface preventing the electroplating solution from penetrating the interface of the patterned dry film resist and the conductive structure during the formation of the conductive plug. The patterned dry film resist is removed from the conductive structure. The conductive plug is reflowed to form the bump structure.

摘要翻译： 通过使用电镀液形成凸点结构的方法，包括以下步骤。 提供具有上覆导电结构的基板。 在导电结构上形成图案化的干膜抗蚀剂。 图案化的干膜抗蚀剂具有暴露导电结构的一部分的沟槽。 在界面处附着在导电结构上的图案化的干膜抗蚀剂。 通过增加图案化的干膜抗蚀剂在界面处的导电结构的粘附性的处理来处理该结构。 通过使用电镀溶液，导电插塞在沟槽内的导电结构的暴露部分之上。 图案化的干膜抗蚀剂在界面处增加了对导电结构的粘附，防止电镀溶液在形成导电插塞期间渗透图案化的干膜抗蚀剂和导电结构的界面。 从导电结构去除图案化的干膜抗蚀剂。 导电塞被回流以形成凸块结构。