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1.发明授权Apparatus and methods for characterizing floating body effects in SOI devices 失效用于表征SOI器件中浮体效应的装置和方法公开(公告)号：US06774395B1
公开(公告)日：2004-08-10
申请号：US10345007
申请日：2003-01-15
申请人： Hung-Jen Lin , W Eugene Hill , Mario M. Pelella , Chern-Jann Lee , Srikanth Sundararajan , Siu May Ho
发明人： Hung-Jen Lin , W Eugene Hill , Mario M. Pelella , Chern-Jann Lee , Srikanth Sundararajan , Siu May Ho
IPC分类号： H01L2358
CPC分类号： H01L22/34
摘要： Methods are described for characterizing floating body delay effects in SOI wafers comprising providing a pulse edge to a floating body and a tied body chain in the wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects according to the stored tied body chain data. Test apparatus are also described comprising a floating body chain including a plurality of series connected floating body inverters or NAND gates fabricated in the wafer and a tied body chain comprising a plurality of series connected tied body devices to in the wafer. Storage devices are coupled with the tied body devices and with one or more of the floating body devices and operate to store tied body chain data from the tied body devices according to one or more signals from floating body chain.
摘要翻译： 描述了用于表征SOI晶片中的浮体延迟效应的方法，包括向晶片中的浮体和绑定的主体链提供脉冲边缘，根据一个或多个浮体装置存储绑定的身体链数据，并表征浮动 根据存储的绑定的身体链数据的身体延迟效应。 还描述了测试装置，其包括浮体体链，其包括在晶片中制造的多个串联连接的浮体反相器或NAND门，以及包括多个串联连接的绑定体装置的晶片的绑定体链。 存储装置与绑定的身体装置和一个或多个浮体装置相耦合，并根据来自浮体的一个或多个信号，操作以从捆绑的身体装置中存储绑定的身体链数据。
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2.发明授权Wafer level global bitmap characterization in integrated circuit technology development 有权晶圆级全局位图表征在集成电路技术开发中公开(公告)号：US07137085B1
公开(公告)日：2006-11-14
申请号：US10858739
申请日：2004-06-01
申请人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
发明人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31718 , G01R31/318511
摘要： A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.
摘要翻译： 用于晶片级全局位图表征的系统和方法包括从半导体晶片确定芯片级缺陷数据位图，以及将芯片级缺陷数据位图合并到表征基本上整个晶片故障配置的全局晶片级位图中。 然后分析全球晶圆级位图并与其他全球晶圆级位图进行比较，以开发相关性，并开发全球晶圆级位图定义，用于进行晶圆到晶片，船对船和批次位图中的至少一个， 基于全球晶圆级位图定义的批量处理分析。
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3.发明授权Method and system for storing and retrieving semiconductor tester information 有权存储和检索半导体测试仪信息的方法和系统公开(公告)号：US08725748B1
公开(公告)日：2014-05-13
申请号：US10929038
申请日：2004-08-27
IPC分类号： G06F17/30
CPC分类号： G01R31/318314
摘要： A tester information tester information processing system provides test equipment for generating test data. A markup language encoder connected to the test equipment encodes the test data for storage in an object-oriented database management system connected to the markup language encoder, and a user interface is operatively connected to the object-oriented database management system for retrieval of the test data.
摘要翻译： 测试仪信息测试仪信息处理系统提供测试设备生成测试数据。 连接到测试设备的标记语言编码器对连接到标记语言编码器的面向对象的数据库管理系统中存储的测试数据进行编码，并且用户界面可操作地连接到面向对象的数据库管理系统以检索测试 数据。
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公开(公告)号：US07634127B1
公开(公告)日：2009-12-15
申请号：US10884333
申请日：2004-07-01
CPC分类号： G01R31/318511 , G01R31/2894 , G06T11/206
摘要： A method and system for fault isolation in semiconductor with devices thereon includes determining test data from a plurality of semiconductor devices and creating a failure bitmap of locations of the plurality of semiconductor devices and test data in a vector graphic CAD format. The vector graphic CAD format allows storage of test data on multiple layers.
摘要翻译： 一种用于其中装置的半导体中的故障隔离的方法和系统，包括：确定来自多个半导体器件的测试数据，并以向量图形CAD格式创建多个半导体器件的位置以及测试数据的故障位图。 矢量图形CAD格式允许在多层存储测试数据。
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