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    Apparatus for analyzing a substrate employing a copper decoration
    2.
    发明授权
    Apparatus for analyzing a substrate employing a copper decoration 失效
    用于分析使用铜装饰的基板的装置

    公开(公告)号：US06919214B2

    公开(公告)日：2005-07-19

    申请号：US10688954

    申请日：2003-10-21

    申请人： Gi-Jung Kim ,  Kyoo-Chul Cho ,  Tae-Yeol Heo ,  Sook-Hyun Park

    发明人： Gi-Jung Kim ,  Kyoo-Chul Cho ,  Tae-Yeol Heo ,  Sook-Hyun Park

    IPC分类号： G01N33/00 ,  H01L21/66 ,  H01L21/00

    CPC分类号： H01L22/24 ,  G01N2033/0095

    摘要： An apparatus for analyzing a substrate employing a copper decoration includes a bath having at least two receiving containers for receiving electrolytes, slots formed at insides of the receiving containers for receiving substrates to be analyzed in a direction that is normal to a bottom face of the bath, lower copper plates provided in the receiving containers, the lower copper plates making contact with entire rear faces of the substrates received in the receiving containers, upper copper plates provided in the receiving containers, each of the upper copper plates corresponding to a respective one of the lower copper plates, and separated from front faces of the substrates, and a power source connected to the upper copper plates and the lower copper plates for providing voltages to the same. A plurality of substrates may be simultaneously analyzed using one apparatus thereby greatly reducing an amount of time required for the analysis.

    摘要翻译： 用于分析使用铜装饰的基板的装置包括具有至少两个用于接收电解质的接收容器的浴槽，在接收容器的内侧形成的槽，用于接收正常于浴底面的方向分析的基板 设置在接收容器中的下铜板，与接收容器中容纳的基板的整个后表面接触的下铜板，设置在接收容器中的上铜板，每个上铜板对应于 下铜板，并且与基板的前表面分离，以及连接到上铜板和下铜板的电源，用于向其提供电压。 可以使用一个装置同时分析多个基板，从而大大减少了分析所需的时间量。

    Polishing pad of a chemical mechanical polishing apparatus and method of manufacturing the same
    5.
    发明申请
    Polishing pad of a chemical mechanical polishing apparatus and method of manufacturing the same 有权
    化学机械抛光装置的抛光垫及其制造方法

    公开(公告)号：US20070197143A1

    公开(公告)日：2007-08-23

    申请号：US11706241

    申请日：2007-02-15

    申请人： Young-Sam Lim ,  Young-Nam Kim ,  Gi-Jung Kim

    发明人： Young-Sam Lim ,  Young-Nam Kim ,  Gi-Jung Kim

    IPC分类号： B24B1/00 ,  B24D11/00

    CPC分类号： B24B37/24 ,  B24D18/0063

    摘要： The surface(s) of a polishing pad for polishing an object has a first portion including hydrophilic material and a second portion including hydrophobic material. The first portion of the polishing surface is located in a first region of the polishing pad and the second portion of the polishing surface is located in a second region of the polishing pad juxtaposed with the first region in the radial direction of the pad. The hydrophilic material may be a polymer resin that contains hydrophilic functional groups having OH and/or ═O at bonding sites of the polymer. The hydrophobic material may be a polymer resin that contains hydrophobic functional groups having H and/or F at bonding sites of the polymer. The polishing pad is manufactured by extruding respective lines of the hydrophilic and hydrophobic materials. The extruders and a backing are moved relative to each other such that the lines form concentric rings of the hydrophilic and hydrophobic materials.

    摘要翻译： 用于抛光物体的抛光垫的表面具有包括亲水材料的第一部分和包括疏水材料的第二部分。 抛光表面的第一部分位于抛光垫的第一区域中，并且抛光表面的第二部分位于抛光垫的与垫的径向方向上与第一区域并置的第二区域中。 亲水材料可以是聚合物树脂，其在聚合物的键合位置含有具有OH和/或-O的亲水性官能团。 疏水性材料可以是在聚合物的结合位置含有H和/或F的疏水官能团的聚合物树脂。 抛光垫通过挤出亲水和疏水材料的相应线来制造。 挤出机和背衬相对于彼此移动，使得线形成亲水和疏水材料的同心环。

    Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
    7.
    发明授权
    Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination 有权
    具有不对称边缘轮廓的半导体晶片，其通过抑制颗粒污染而促进高产量处理

    公开(公告)号：US07258931B2

    公开(公告)日：2007-08-21

    申请号：US10601475

    申请日：2003-06-23

    申请人： Gi-Jung Kim ,  Woo-Serk Kim ,  Sang-Mun Chon ,  Tae-Yeol Heo

    发明人： Gi-Jung Kim ,  Woo-Serk Kim ,  Sang-Mun Chon ,  Tae-Yeol Heo

    IPC分类号： B32B9/00 ,  H01L29/06

    CPC分类号： H01L21/02021 ,  Y10T428/12674

    摘要： Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations adjacent a peripheral edge thereof. These edges profiles are also configured to inhibit redeposition of residue particulates on the top surfaces of the wafers during semiconductor processing steps. Such steps may include surface cleaning and rinsing steps that may include passing a cleaning or rinsing solution across a wafer or batch of wafers that are held by a cartridge and submerged in the solution.

    摘要翻译： 半导体晶片利用不对称边缘轮廓（EP）来促进更高产量的半导体器件处理。 这些边缘轮廓被配置为减小可能在与其周边边缘相邻的位置处在半导体晶片的顶表面上形成的薄膜残余物的体积。 这些边缘轮廓也被配置为在半导体处理步骤期间抑制残余颗粒在晶片的顶表面上的再沉积。 这样的步骤可以包括表面清洁和冲洗步骤，其可以包括将清洁或冲洗溶液通过由盒保持并浸没在溶液中的晶片或一批晶片。

    Susceptor and deposition apparatus including the same
    8.
    发明申请
    Susceptor and deposition apparatus including the same 审中-公开
    受体和包括其的沉积装置

    公开(公告)号：US20050016470A1

    公开(公告)日：2005-01-27

    申请号：US10898306

    申请日：2004-07-26

    申请人： Tae-Soo Kang ,  Soo-Yeol Choi ,  Kyoo-Chul Cho ,  Gi-Jung Kim ,  Jin-Ho Kim ,  Tae-Yeol Heo

    发明人： Tae-Soo Kang ,  Soo-Yeol Choi ,  Kyoo-Chul Cho ,  Gi-Jung Kim ,  Jin-Ho Kim ,  Tae-Yeol Heo

    IPC分类号： H01L21/205 ,  C23C16/00 ,  C23C16/458 ,  C30B25/12 ,  C30B31/14

    CPC分类号： C23C16/4584 ,  C30B25/12 ,  C30B31/14

    摘要： A susceptor for use in a deposition apparatus includes a recess in which a wafer is received, and a stress-reducing bumper disposed along the side of the recess. The stress-reducing bumper is of material having ductility at a relatively high temperature. Therefore, when the wafer contacts the stress-reducing bumper, such as may occur due to thermal expansion of the wafer during processing, the force of the impact on the wafer is minimized by an elastic deformation of the stress-reducing bumper. As a result, defects, such as slip dislocations at the outer peripheral edge of the wafer, are prevented.

    摘要翻译： 用于沉积设备的感受体包括其中容纳晶片的凹部和沿着凹部的侧面设置的减小应力的保险杠。 减压保险杠是在较高温度下具有延性的材料。 因此，当晶片接触减压保险杠时，例如由于晶片在加工过程中的热膨胀而可能发生的，通过减小应力的保险杠的弹性变形使得对晶片的冲击力最小化。 结果，防止了晶片外周边缘处的滑移位错等缺陷。

    Polishing pad of a chemical mechanical polishing apparatus and method of manufacturing the same
    9.
    发明授权
    Polishing pad of a chemical mechanical polishing apparatus and method of manufacturing the same 有权
    化学机械抛光装置的抛光垫及其制造方法

    公开(公告)号：US07815496B2

    公开(公告)日：2010-10-19

    申请号：US11706241

    申请日：2007-02-15

    申请人： Young-Sam Lim ,  Young-Nam Kim ,  Gi-Jung Kim

    发明人： Young-Sam Lim ,  Young-Nam Kim ,  Gi-Jung Kim

    IPC分类号： B24D11/00

    CPC分类号： B24B37/24 ,  B24D18/0063

    摘要： The surface(s) of a polishing pad for polishing an object has a first portion including hydrophilic material and a second portion including hydrophobic material. The first portion of the polishing surface is located in a first region of the polishing pad and the second portion of the polishing surface is located in a second region of the polishing pad juxtaposed with the first region in the radial direction of the pad. The hydrophilic material may be a polymer resin that contains hydrophilic functional groups having OH and/or ═O at bonding sites of the polymer. The hydrophobic material may be a polymer resin that contains hydrophobic functional groups having H and/or F at bonding sites of the polymer. The polishing pad is manufactured by extruding respective lines of the hydrophilic and hydrophobic materials. The extruders and a backing are moved relative to each other such that the lines form concentric rings of the hydrophilic and hydrophobic materials.

    摘要翻译： 用于抛光物体的抛光垫的表面具有包括亲水材料的第一部分和包括疏水材料的第二部分。 抛光表面的第一部分位于抛光垫的第一区域中，并且抛光表面的第二部分位于抛光垫的与垫的径向方向上与第一区域并置的第二区域中。 亲水材料可以是在聚合物的键合位置处含有OH和/或= O的亲水性官能团的聚合物树脂。 疏水性材料可以是在聚合物的结合位置含有H和/或F的疏水官能团的聚合物树脂。 抛光垫通过挤出亲水和疏水材料的相应线来制造。 挤出机和背衬相对于彼此移动，使得线形成亲水和疏水材料的同心环。

    Semiconductor wafer having identification indication
    10.
    发明授权
    Semiconductor wafer having identification indication 失效
    具有识别指示的半导体晶片

    公开(公告)号：US07372150B2

    公开(公告)日：2008-05-13

    申请号：US10684343

    申请日：2003-10-10

    申请人： Sam-Jong Choi ,  Gi-Jung Kim ,  Kyoo-Chul Cho ,  Yeon-Sook Kim ,  Shin-Hyeok Han ,  Hoe-Sik Chung

    发明人： Sam-Jong Choi ,  Gi-Jung Kim ,  Kyoo-Chul Cho ,  Yeon-Sook Kim ,  Shin-Hyeok Han ,  Hoe-Sik Chung

    IPC分类号： H01L23/04

    CPC分类号： H01L23/544 ,  H01L29/0657 ,  H01L2223/54406 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.

    摘要翻译： 提供了包括识别指示的半导体晶片。 晶片包括具有上表面区域和下表面区域的凸边缘。 识别指示位于设置在凸缘的下侧表面上的标记区域中。 下侧表面具有标记区域所在的宽区域。 该宽区域的宽度比晶片的上侧面宽，因此晶片侧面的截面不对称。 利用本发明，半导体晶片的整个顶表面可以用于半导体芯片区域，并且当识别位于晶片的顶表面上时，可防止与识别指示的不均匀性有关的制造问题。