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18 条记录 (耗时 0.028 秒)

    Susceptor and deposition apparatus including the same
    1.
    发明申请
    Susceptor and deposition apparatus including the same 审中-公开
    受体和包括其的沉积装置

    公开(公告)号：US20050016470A1

    公开(公告)日：2005-01-27

    申请号：US10898306

    申请日：2004-07-26

    申请人： Tae-Soo Kang ,  Soo-Yeol Choi ,  Kyoo-Chul Cho ,  Gi-Jung Kim ,  Jin-Ho Kim ,  Tae-Yeol Heo

    发明人： Tae-Soo Kang ,  Soo-Yeol Choi ,  Kyoo-Chul Cho ,  Gi-Jung Kim ,  Jin-Ho Kim ,  Tae-Yeol Heo

    IPC分类号： H01L21/205 ,  C23C16/00 ,  C23C16/458 ,  C30B25/12 ,  C30B31/14

    CPC分类号： C23C16/4584 ,  C30B25/12 ,  C30B31/14

    摘要： A susceptor for use in a deposition apparatus includes a recess in which a wafer is received, and a stress-reducing bumper disposed along the side of the recess. The stress-reducing bumper is of material having ductility at a relatively high temperature. Therefore, when the wafer contacts the stress-reducing bumper, such as may occur due to thermal expansion of the wafer during processing, the force of the impact on the wafer is minimized by an elastic deformation of the stress-reducing bumper. As a result, defects, such as slip dislocations at the outer peripheral edge of the wafer, are prevented.

    摘要翻译： 用于沉积设备的感受体包括其中容纳晶片的凹部和沿着凹部的侧面设置的减小应力的保险杠。 减压保险杠是在较高温度下具有延性的材料。 因此，当晶片接触减压保险杠时，例如由于晶片在加工过程中的热膨胀而可能发生的，通过减小应力的保险杠的弹性变形使得对晶片的冲击力最小化。 结果，防止了晶片外周边缘处的滑移位错等缺陷。

    Apparatus for analyzing a substrate employing a copper decoration
    2.
    发明授权
    Apparatus for analyzing a substrate employing a copper decoration 失效
    用于分析使用铜装饰的基板的装置

    公开(公告)号：US06919214B2

    公开(公告)日：2005-07-19

    申请号：US10688954

    申请日：2003-10-21

    申请人： Gi-Jung Kim ,  Kyoo-Chul Cho ,  Tae-Yeol Heo ,  Sook-Hyun Park

    发明人： Gi-Jung Kim ,  Kyoo-Chul Cho ,  Tae-Yeol Heo ,  Sook-Hyun Park

    IPC分类号： G01N33/00 ,  H01L21/66 ,  H01L21/00

    CPC分类号： H01L22/24 ,  G01N2033/0095

    摘要： An apparatus for analyzing a substrate employing a copper decoration includes a bath having at least two receiving containers for receiving electrolytes, slots formed at insides of the receiving containers for receiving substrates to be analyzed in a direction that is normal to a bottom face of the bath, lower copper plates provided in the receiving containers, the lower copper plates making contact with entire rear faces of the substrates received in the receiving containers, upper copper plates provided in the receiving containers, each of the upper copper plates corresponding to a respective one of the lower copper plates, and separated from front faces of the substrates, and a power source connected to the upper copper plates and the lower copper plates for providing voltages to the same. A plurality of substrates may be simultaneously analyzed using one apparatus thereby greatly reducing an amount of time required for the analysis.

    摘要翻译： 用于分析使用铜装饰的基板的装置包括具有至少两个用于接收电解质的接收容器的浴槽，在接收容器的内侧形成的槽，用于接收正常于浴底面的方向分析的基板 设置在接收容器中的下铜板，与接收容器中容纳的基板的整个后表面接触的下铜板，设置在接收容器中的上铜板，每个上铜板对应于 下铜板，并且与基板的前表面分离，以及连接到上铜板和下铜板的电源，用于向其提供电压。 可以使用一个装置同时分析多个基板，从而大大减少了分析所需的时间量。

    Apparatus for inspecting a surface and methods thereof
    3.
    发明申请
    Apparatus for inspecting a surface and methods thereof 审中-公开
    用于检查表面的装置及其方法

    公开(公告)号：US20050259246A1

    公开(公告)日：2005-11-24

    申请号：US11133367

    申请日：2005-05-20

    申请人： Tae-Soo Kang ,  Kyoo-Chul Cho ,  Soo-Yeol Choi ,  Sam-Dong Choi

    发明人： Tae-Soo Kang ,  Kyoo-Chul Cho ,  Soo-Yeol Choi ,  Sam-Dong Choi

    IPC分类号： H01L21/66 ,  G01N21/47 ,  G01N21/88 ,  G01N21/95

    CPC分类号： G01N21/47 ,  G01N21/9501

    摘要： An apparatus and method for detecting a surface status. The method includes generating first and second pulse sequences and irradiating the first and second pulse sequences into a given surface. Light from the first and second pulses may be scattered by the given surface and analyzed to determine the status of the given surface. The apparatus includes a device for generating pulses which contact a given surface at different incident angles. The light scattered from the pulses may be analyzed at a determining part to determine a status of the given surface. In another embodiment, the method includes generating first and second pulse sequences and adjusting a path of at least a portion of at least one of the first and second pulse sequences such that the first and second pulse sequences are incident upon a given surface at different incident angles.

    摘要翻译： 一种用于检测表面状态的装置和方法。 该方法包括产生第一和第二脉冲序列并将第一和第二脉冲序列照射到给定的表面中。 来自第一和第二脉冲的光可以被给定的表面散射并且被分析以确定给定表面的状态。 该装置包括用于产生以不同入射角接触给定表面的脉冲的装置。 可以在确定部分分析从脉冲散射的光以确定给定表面的状态。 在另一个实施例中，该方法包括产生第一和第二脉冲序列并且调整第一和第二脉冲序列中的至少一个的至少一部分的路径，使得第一和第二脉冲序列在不同事件处入射到给定表面上 角度。

    Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method
    4.
    发明申请
    Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method 审中-公开
    通过该方法制造半导体存储器件和半导体存储器件的方法

    公开(公告)号：US20080246077A1

    公开(公告)日：2008-10-09

    申请号：US12012592

    申请日：2008-02-04

    申请人： Young-Soo Park ,  Sam-Jong Choi ,  Kyoo-Chul Cho ,  Tae-Soo Kang

    发明人： Young-Soo Park ,  Sam-Jong Choi ,  Kyoo-Chul Cho ,  Tae-Soo Kang

    IPC分类号： H01L27/108 ,  H01L21/425

    CPC分类号： H01L29/7881 ,  B82Y10/00 ,  H01L21/26506 ,  H01L29/40114 ,  H01L29/42332

    摘要： In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure.

    摘要翻译： 在通过该方法制造半导体存储器件和半导体存储器件的方法中，该方法包括形成包括具有离子注入层的第一介电层和没有离子注入层的第二电介质层的多层电介质结构， 在半导体衬底上; 通过热处理多层电介质结构，通过离子注入层的离子扩散来在第一和第二电介质层中形成纳米晶体; 以及在所述多层电介质结构上形成栅电极。

    Semiconductor wafer and method of fabricating the same
    5.
    发明授权
    Semiconductor wafer and method of fabricating the same 有权
    半导体晶片及其制造方法

    公开(公告)号：US07675091B2

    公开(公告)日：2010-03-09

    申请号：US11463137

    申请日：2006-08-08

    申请人： Young-Soo Park ,  Kyoo-Chul Cho ,  Shin-Hyeok Han ,  Tae-Soo Kang

    发明人： Young-Soo Park ,  Kyoo-Chul Cho ,  Shin-Hyeok Han ,  Tae-Soo Kang

    IPC分类号： H01L29/80

    CPC分类号： H01L29/045 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78687 ,  H01L29/78696

    摘要： Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

    摘要翻译： 公开了半导体晶片及其制造方法。 半导体晶片由在基底基板上的绝缘层上形成的半导体层构成。 半导体层包括以第一晶体取向组织的表面区域和以第二晶体取向组织的另一表面区域。 带有单元元件的半导体器件的性能随着载流子的增强而被使用以高结晶取向的高迁移率激活的电荷。 半导体晶片通过在第一晶体取向的平面上形成具有第二晶体取向的半导体层，生长外延层，在外延层上形成绝缘层，然后将绝缘层接合到基底来完成。

    Semiconductor device and method for forming the same
    6.
    发明授权
    Semiconductor device and method for forming the same 有权
    半导体装置及其形成方法

    公开(公告)号：US07573123B2

    公开(公告)日：2009-08-11

    申请号：US11775130

    申请日：2007-07-09

    申请人： Young-Soo Park ,  Kyoo-Chul Cho ,  Hee-Sung Kim ,  Tae-Soo Kang ,  Sam-Jong Choi

    发明人： Young-Soo Park ,  Kyoo-Chul Cho ,  Hee-Sung Kim ,  Tae-Soo Kang ,  Sam-Jong Choi

    IPC分类号： H01L29/04 ,  H01L31/036

    CPC分类号： H01L21/76254 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795

    摘要： Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.

    摘要翻译： 提供半导体器件及其形成方法。 在一个实施例中，半导体器件包括半导体层，第一和第二半导体鳍片，绝缘层和鳍间连接构件。 第一和第二半导体散热片放置在半导体层上，具有不同的晶体方向。 第一半导体鳍状物与半导体层连接，具有与半导体层相同的晶体方向。 绝缘层介于第二半导体鳍片和半导体层之间，并且具有插入第一半导体鳍片的开口。 翅片间连接构件将第一半导体翅片和第二半导体翅片在绝缘层上连接起来。

    Semiconductor wafer having identification indication
    8.
    发明授权
    Semiconductor wafer having identification indication 失效
    具有识别指示的半导体晶片

    公开(公告)号：US07372150B2

    公开(公告)日：2008-05-13

    申请号：US10684343

    申请日：2003-10-10

    申请人： Sam-Jong Choi ,  Gi-Jung Kim ,  Kyoo-Chul Cho ,  Yeon-Sook Kim ,  Shin-Hyeok Han ,  Hoe-Sik Chung

    发明人： Sam-Jong Choi ,  Gi-Jung Kim ,  Kyoo-Chul Cho ,  Yeon-Sook Kim ,  Shin-Hyeok Han ,  Hoe-Sik Chung

    IPC分类号： H01L23/04

    CPC分类号： H01L23/544 ,  H01L29/0657 ,  H01L2223/54406 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.

    摘要翻译： 提供了包括识别指示的半导体晶片。 晶片包括具有上表面区域和下表面区域的凸边缘。 识别指示位于设置在凸缘的下侧表面上的标记区域中。 下侧表面具有标记区域所在的宽区域。 该宽区域的宽度比晶片的上侧面宽，因此晶片侧面的截面不对称。 利用本发明，半导体晶片的整个顶表面可以用于半导体芯片区域，并且当识别位于晶片的顶表面上时，可防止与识别指示的不均匀性有关的制造问题。

    Organic aluminum precursor and method of manufacturing a metal wiring using the same
    9.
    发明申请
    Organic aluminum precursor and method of manufacturing a metal wiring using the same 失效
    有机铝前体及其制造方法

    公开(公告)号：US20070071893A1

    公开(公告)日：2007-03-29

    申请号：US11524295

    申请日：2006-09-21

    申请人： Jung-Ho Lee ,  Jung-Sik Choi ,  Jun-Hyun Cho ,  Youn-Joung Cho ,  Tae-Sung Kim ,  Mi-Ae Kim ,  Kyoo-Chul Cho

    发明人： Jung-Ho Lee ,  Jung-Sik Choi ,  Jun-Hyun Cho ,  Youn-Joung Cho ,  Tae-Sung Kim ,  Mi-Ae Kim ,  Kyoo-Chul Cho

    IPC分类号： C23C16/00 ,  C07F5/06

    CPC分类号： C07F5/066 ,  C07F5/062 ,  C23C16/20

    摘要： In a method of manufacturing a metal wiring, an organic aluminum precursor that includes aluminum as a central metal is applied to a substrate. The organic aluminum precursor applied to the substrate is thermally decomposed to form aluminum. The aluminum is deposited on the substrate to form an aluminum wiring having a low resistance. The organic aluminum precursor includes a chemical structure in accordance with one of the chemical formulae: wherein R1, R2, R3, R4 and R5 are independently H or a C1-C5 alkyl functional group, n is an integer of 1 to 5, x is 1 or 2, and y is 0 or 1, or wherein R1, R2, R3, R4 R5, R6, R7 and R8 are independently H or a C1-C5 alkyl functional group, and Y is boron.

    摘要翻译： 在制造金属布线的方法中，将包含铝作为中心金属的有机铝前体施加到基板上。 施加到基材上的有机铝前体热分解形成铝。 铝沉积在基板上以形成具有低电阻的铝布线。 有机铝前体包括根据以下化学式之一的化学结构：其中R 1，R 2，R 3，R 3， R 4和R 5独立地是H或C 1 -C 5烷基官能团，n是整数 1至5，x为1或2，y为0或1，或其中R 1，R 2，R 3，R R 5，R 6，R 7和R 8独立地是H 或C 1 -C 5烷基官能团，Y是硼。