公开(公告)号：US09048210B2

公开(公告)日：2015-06-02

申请号：US13550032

申请日：2012-07-16

申请人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

发明人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

IPC分类号： H01L29/36 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/36 ,  H01L29/6634 ,  H01L29/7397

摘要： A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.

摘要翻译： 晶体管包括器件部分和集电极层。 器件部分位于半导体衬底的第一侧，并且包括栅极和发射极。 集电极层位于半导体衬底的与第一侧相对的第二侧上。 集电极层是杂质掺杂的外延层，并具有非正态分布的掺杂分布。

公开(公告)号：US20130200427A1

公开(公告)日：2013-08-08

申请号：US13550032

申请日：2012-07-16

申请人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

发明人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/36 ,  H01L29/6634 ,  H01L29/7397

摘要： A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.

摘要翻译： 晶体管包括器件部分和集电极层。 器件部分位于半导体衬底的第一侧，并且包括栅极和发射极。 集电极层位于半导体衬底的与第一侧相对的第二侧上。 集电极层是杂质掺杂的外延层，并具有非正态分布的掺杂分布。

公开(公告)号：US08835985B2

公开(公告)日：2014-09-16

申请号：US13208671

申请日：2011-08-12

申请人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

发明人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

IPC分类号： H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/408 ,  H01L29/66462

摘要： According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.

摘要翻译： 根据示例性实施例，功率电子器件包括第一半导体层，第一半导体层的第一表面上的第二半导体层以及第二半导体层上的源极，漏极和栅极。 源极，漏极和栅极彼此分开。 电力电子设备还包括在第一半导体层和第二半导体层之间的界面处的二维电子气体（2DEG）区域，栅极上的第一绝缘层和与第一绝缘层相邻的第二绝缘层。 第一绝缘层具有第一介电常数，第二绝缘层具有小于第一介电常数的第二介电常数。

公开(公告)号：US08790998B2

公开(公告)日：2014-07-29

申请号：US12588828

申请日：2009-10-29

申请人： Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

发明人： Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

IPC分类号： H01L21/302 ,  H01L21/336 ,  H01L21/84 ,  H01L21/20 ,  H01L29/12 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/125 ,  B82Y10/00 ,  H01L29/127 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696 ,  Y10T156/10 ,  Y10T156/1082

摘要： Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.

摘要翻译： 示例性实施例涉及形成核 - 壳结构的方法。 根据一种方法，在基板上限定形成芯 - 壳结构的区域，并且可以在限定区域中顺序堆叠芯层和壳层。 第一壳层可以进一步形成在衬底和芯之间。 当核心层和壳层依次层叠在芯 - 壳区域中时，该方法还可以包括在基板上形成凹槽，形成覆盖凹槽表面的第一壳层，在其表面的凹槽中形成芯 被第一壳层覆盖，并且形成覆盖芯的第二壳层。

公开(公告)号：US08508194B2

公开(公告)日：2013-08-13

申请号：US12923857

申请日：2010-10-12

申请人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

发明人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

IPC分类号： G05F1/10

CPC分类号： H03K17/6871 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H02M2001/0074 ,  H03K2217/0081

摘要： Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.

摘要翻译： 提供一种半导体器件，其可以包括具有负阈值电压的开关器件，以及电源端子和接地端子之间的驱动单元，并且提供用于驱动开关器件的驱动电压。 开关器件可以连接到具有大于从接地端子提供的接地电压的虚拟接地电压的虚拟接地节点，并且当驱动电压和虚拟接地电压之间的差大于负值时，可以导通 阈值电压。

公开(公告)号：US20130032816A1

公开(公告)日：2013-02-07

申请号：US13431397

申请日：2012-03-27

申请人： In-jun Hwang ,  Hyuk-soon Choi ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  Ki-ha Hong ,  Jai-kwang Shin

发明人： In-jun Hwang ,  Hyuk-soon Choi ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  Ki-ha Hong ,  Jai-kwang Shin

IPC分类号： H01L29/20 ,  H01L21/335 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7787

摘要： High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer.

公开(公告)号：US20120088341A1

公开(公告)日：2012-04-12

申请号：US13178902

申请日：2011-07-08

申请人： Hyuk-soon Choi ,  Jung-hee Lee ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  In-jun Hwang ,  Ki-ha Hong ,  Ki-sik Im ,  Ki-won Kim ,  Dong-seok Kim

发明人： Hyuk-soon Choi ,  Jung-hee Lee ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  In-jun Hwang ,  Ki-ha Hong ,  Ki-sik Im ,  Ki-won Kim ,  Dong-seok Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/66462 ,  H01L21/0254 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/7787

摘要： The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

摘要翻译： 所述方法可以包括在衬底上形成第一材料层，增加第一材料层的电阻，以及在第一材料层上形成彼此间隔开的源图案和漏极图案，带隙为 源极和漏极图案大于第一材料层的带隙。

公开(公告)号：US20110068370A1

公开(公告)日：2011-03-24

申请号：US12923126

申请日：2010-09-03

申请人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

发明人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/207 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.

摘要翻译： 包括二维电子气体（2DEG）通道的电力电子装置及其制造方法。 电力电子设备包括用于形成2DEG通道的下部和上部材料层，以及与上部材料层的上表面接触的栅极。 2DEG通道的栅极下方的区域是2DEG的密度减小或为零的截止区域。 整个上部材料层可以是连续的并且可以具有均匀的厚度。 在栅极下方的上部材料层的区域包含用于减少或消除下部和上部材料层之间的晶格常数差的杂质。

公开(公告)号：US08513705B2

公开(公告)日：2013-08-20

申请号：US12923126

申请日：2010-09-03

申请人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

发明人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/207 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.

摘要翻译： 包括二维电子气体（2DEG）通道的电力电子装置及其制造方法。 电力电子设备包括用于形成2DEG通道的下部和上部材料层，以及与上部材料层的上表面接触的栅极。 2DEG通道的栅极下方的区域是2DEG的密度减小或为零的截止区域。 整个上部材料层可以是连续的并且可以具有均匀的厚度。 在栅极下方的上部材料层的区域包含用于减少或消除下部和上部材料层之间的晶格常数差的杂质。

公开(公告)号：US08480959B2

公开(公告)日：2013-07-09

申请号：US13065000

申请日：2011-05-02

申请人： Ki-ha Hong ,  Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin

发明人： Ki-ha Hong ,  Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin

IPC分类号： G01N27/04 ,  G01N30/62

CPC分类号： G01N29/036 ,  G01N2291/0257 ,  Y10S977/957

摘要： Provided is a chemical sensor that may include a first electrode on a substrate, a sensing member covering the first electrode on the substrate, and a plurality of second electrodes on a surface of the sensing member exposing the surface of the sensing member. The chemical sensor may be configured to measure the change in electrical characteristics when a compound to be sensed is adsorbed on the sensing member. Provided also is a chemical sensor array including an array of chemical sensors.

摘要翻译： 提供了一种化学传感器，其可以包括在基板上的第一电极，覆盖基板上的第一电极的感测构件和暴露感测构件的表面的感测构件的表面上的多个第二电极。 化学传感器可以被配置为当要感测的化合物吸附在感测构件上时测量电特性的变化。 还提供了包括化学传感器阵列的化学传感器阵列。