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    Integrated circuit having lightly doped expitaxial collector layer surrounding base and emitter elements and heavily doped buried collector larger in contact with the base element
    2.
    发明授权
    Integrated circuit having lightly doped expitaxial collector layer surrounding base and emitter elements and heavily doped buried collector larger in contact with the base element 失效
    具有轻型收集层的集成电路环绕基座和发射元件以及与基座元件接触的重型埋式收集器较大

    公开(公告)号：US3638081A

    公开(公告)日：1972-01-25

    申请号：US3638081D

    申请日：1968-08-13

    Applicant: IBM

    Inventor： LLOYD ROBERT H F

    IPC: H01L21/74 ,  H01L27/07 ,  H01L29/08 ,  H01L19/00

    CPC classification number: H01L21/743 ,  H01L27/0772 ,  H01L29/0821 ,  Y10S148/037 ,  Y10S148/04 ,  Y10S148/049 ,  Y10S148/085

    Abstract: An integrated circuit is provided in which a heavily doped buried layer within the collector of a transistor extends into contact with the base thereof to form the major portion of the collector-base junction. The buried layer enhances the current gain bandwidth by minimizing the width of the collector-base depletion region and the shift thereof into the collector for high-current densities. The effects of capacitances at the collector-base junction and at the junctions of resistors and isolating walls adjacent the transistor are minimized by a lightly doped epitaxial layer within the collector of the transistor.

    Abstract translation: 提供一种集成电路，其中在晶体管的集电极内的重掺杂掩埋层延伸成与其基极接触以形成集电极 - 基极结的主要部分。 掩埋层通过最小化集电极 - 基极耗尽区的宽度及其对于高电流密度的集电极的偏移来增强电流增益带宽。 通过晶体管的集电极内的轻掺杂的外延层，在集电极 - 基极结和电阻器和邻近晶体管的隔离壁的接合处的电容的影响被最小化。

    Integrated clamping circuit
    3.
    发明授权
    Integrated clamping circuit 失效
    集成钳位电路

    公开(公告)号：US3654530A

    公开(公告)日：1972-04-04

    申请号：US3654530D

    申请日：1970-06-22

    Applicant: IBM

    Inventor： LLOYD ROBERT H F

    IPC: H01L27/07 ,  H01L29/08 ,  H01L19/00

    CPC classification number: H01L29/0821 ,  H01L27/0772

    Abstract: An integrated clamping circuit is provided in which the bulk collector resistance of a transistor is coupled to the base contact by a second collector contact to bias the collector-base junction in response to a potential difference between the base and main collector contacts. The level of collector-base junction bias is determined in part by the size of the auxiliary collector contact and its location relative to a heavily doped buried layer in the collector. The biased transistor conducts in a manner so as to clamp the voltage at the output terminal of an associated electrical device for load current above a threshold value.

    Abstract translation: 提供一种集成钳位电路，其中晶体管的体集电极电阻通过第二集电极触点耦合到基极触点，以响应于基极和主集电极触点之间的电位差来偏置集电极 - 基极结。 集电极 - 基极结偏置的电平部分地由辅助集电极触点的尺寸及其相对于集电极中的重掺杂掩埋层的位置确定。 偏置晶体管以这样的方式导通，以便将相关电气设备的输出端子处的电压钳位以使负载电流高于阈值。

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