公开(公告)号：US3621279A

公开(公告)日：1971-11-16

申请号：US3621279D

申请日：1970-01-28

Applicant: IBM

Inventor： JEN TEH-SEN ,  PRICER WILBUR D ,  VOGL NORBERT G JR

IPC: G11C19/18 ,  H01L27/088 ,  G11C19/00

CPC classification number: G11C19/186 ,  H01L27/088

Abstract: A dynamic shift register is disclosed for providing large capacity storage of digital data information in a small-volume solid-state package. A unique high-density approach is taken, involving a cell comprising n subcells capable of storing n-1 bits of data. The cells are fabricated preferably of field effect transistors embedded in a semiconductor wafer or monolith.

公开(公告)号：US3471839A

公开(公告)日：1969-10-07

申请号：US3471839D

申请日：1965-09-14

Applicant: IBM

Inventor： SIMKINS QUINTON W ,  VOGL NORBERT G JR

IPC: G11C7/00 ,  G11C7/02 ,  G11C11/14 ,  G11B5/00

CPC classification number: G11C7/02 ,  G11C7/00 ,  G11C11/14

公开(公告)号：US3648255A

公开(公告)日：1972-03-07

申请号：US3648255D

申请日：1969-12-31

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  ORDEMANN FRED A JR ,  PRICER WILBUR D ,  VOGL NORBERT G JR

IPC: G11C19/00 ,  G11C19/18 ,  G06F7/34

CPC classification number: G11C19/188 ,  G11C19/00

Abstract: An electronic bulk storage having the characteristics of a sequential access storage device, such as a disk or a drum, but which has a low-access time and a variable instantaneous data rate. Data re stored parallel by word in a plurality of electronically rotatable memory elements selectable by a memory selection matrix. Each element has a feedback loop for recirculating data and when selected, a group of elements is read or written in parallel to a word at a time by electronically rotating the selected memory elements.

Abstract translation: 具有顺序访问存储装置（诸如盘或鼓）但具有低访问时间和可变瞬时数据速率的特征的电子批量存储器。 数据通过字被并行存储在由存储器选择矩阵选择的多个电子可旋转存储元件中。 每个元件具有用于再循环数据的反馈回路，并且当选择时，通过电子地旋转所选择的存储元件，一组元件一次读取或并行写入一个单词。

公开(公告)号：US3626390A

公开(公告)日：1971-12-07

申请号：US3626390D

申请日：1969-11-13

Applicant: IBM

Inventor： CHANG JOSEPH J ,  HO IRVING TZE ,  VOGL NORBERT G JR ,  WU BEVAN P F

IPC: G11C11/411 ,  H01L21/74 ,  H01L27/07 ,  H03K3/288 ,  G11C11/40

CPC classification number: H03K3/288 ,  G11C11/4116 ,  H01L21/74 ,  H01L27/0755 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/136

Abstract: A nondestructive read-integrated circuit memory cell consisting of a pair of cross coupled transistors. The junctions between the collectors of the transistors and the intrinsic epitaxial layer is utilized to provide isolation between the transistors. The transistors are formed by a triple-diffusion process wherein the collector region contacts a buried layer of opposite semiconductivity relative to the semiconductivity of the substrate structure. An epitaxial growth being of the same semiconductivity as the buried layer region is utilized as both a resistive material between the input and the buried layer and to form a diode gradient between the epitaxial region and the collector region of the transistors. The buried region forms a diode junction with the collector regions of the transistor to allow a bilevel operation of the memory cell.