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公开(公告)号：US10797224B2
公开(公告)日：2020-10-06
申请号：US15904189
申请日：2018-02-23
Applicant: IMEC VZW , Katholieke Universiteit Leuven
Inventor： Praveen Raghavan , Davide Francesco Crotti , Raf Appeltans
Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer. The device additionally includes a magnetic tunnel junction (MTJ) device including a bottom layer, a top layer and an MTJ structure arranged between the bottom layer and the top layer, wherein the bottom layer is connected to a bottom layer contact portion of the first set of conductive paths and the top layer is connected to a top layer contact portion of the second or third set of conductive paths. The device further includes a multi-level via extending through the second dielectric layer and the third dielectric layer, between a first via contact portion of the first set of conductive paths and a second via contact portion of the third set of conductive paths, wherein a height of the MTJ device corresponds to, or-is less than, a height of the multi-level via, e.g., wherein the height of the MTJ device corresponds to or is less than a height of the second interconnection level.
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Patent Agency Ranking
公开(公告)号：US20220059760A1
公开(公告)日：2022-02-24
申请号：US17445557
申请日：2021-08-20
Applicant: IMEC vzw
Inventor： Davide Francesco Crotti , Kevin Garello
Abstract: According to an aspect, there is provided a method of forming a magnetic tunneling junction (MTJ) device, including: forming a layer stack including an MTJ layer structure and a spin-orbit torque (SOT) layer below the MTJ layer structure; forming a first etch mask over the layer stack, the first etch mask including a first mask line extending in a first horizontal direction; patterning the layer stack to form an MTJ line extending in the first horizontal direction, the patterning including etching while the first etch mask masks the layer stack, and stopping etching on or above the SOT-layer; forming sidewall spacers on one or both sides of the MTJ line; while the sidewall spacers mask the SOT-layer, etching the SOT-layer to form a patterned layer stack including the MTJ line and a first patterned SOT-layer; forming a second etch mask over the patterned layer stack, the second etch mask including a second mask line extending in a second horizontal direction across the MTJ line; and patterning the patterned layer stack to form a twice patterned SOT-layer, the twice patterned SOT-layer including an SOT-line extending in the second horizontal direction, and to form an MTJ pillar on the SOT-line, the patterning including etching while the second etch mask masks the patterned layer stack.
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公开(公告)号：US10825868B2
公开(公告)日：2020-11-03
申请号：US16234381
申请日：2018-12-27
Applicant: IMEC vzw
Inventor： Romain Delhougne , Davide Francesco Crotti , Gouri Sankar Kar , Luca Di Piazza , Ludovic Goux
IPC: H01L27/24 , H01L27/11597 , H01L45/00
Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.
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公开(公告)号：US11793085B2
公开(公告)日：2023-10-17
申请号：US17445557
申请日：2021-08-20
Applicant: IMEC vzw
Inventor： Davide Francesco Crotti , Kevin Garello
Abstract: According to an aspect, there is provided a method of forming a magnetic tunneling junction (MTJ) device, including: forming a layer stack including an MTJ layer structure and a spin-orbit torque (SOT) layer below the MTJ layer structure; forming a first etch mask over the layer stack, the first etch mask including a first mask line extending in a first horizontal direction; patterning the layer stack to form an MTJ line extending in the first horizontal direction, the patterning including etching while the first etch mask masks the layer stack, and stopping etching on or above the SOT-layer; forming sidewall spacers on one or both sides of the MTJ line; while the sidewall spacers mask the SOT-layer, etching the SOT-layer to form a patterned layer stack including the MTJ line and a first patterned SOT-layer; forming a second etch mask over the patterned layer stack, the second etch mask including a second mask line extending in a second horizontal direction across the MTJ line; and patterning the patterned layer stack to form a twice patterned SOT-layer, the twice patterned SOT-layer including an SOT-line extending in the second horizontal direction, and to form an MTJ pillar on the SOT-line, the patterning including etching while the second etch mask masks the patterned layer stack.
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公开(公告)号：US20190221610A1
公开(公告)日：2019-07-18
申请号：US16234381
申请日：2018-12-27
Applicant: IMEC vzw
Inventor： Romain Delhougne , Davide Francesco Crotti , Gouri Sankar Kar , Luca Di Piazza , Ludovic Goux
IPC: H01L27/24 , H01L45/00 , H01L27/11597
CPC classification number: H01L27/249 , H01L27/11597 , H01L27/2409 , H01L27/2427 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1683
Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.
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公开(公告)号：US20180248111A1
公开(公告)日：2018-08-30
申请号：US15904189
申请日：2018-02-23
Applicant: IMEC VZW , Katholieke Universiteit Leuven
Inventor： Praveen Raghavan , Davide Francesco Crotti , Raf Appeltans
Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer. The device additionally includes a magnetic tunnel junction (MTJ) device including a bottom layer, a top layer and an MTJ structure arranged between the bottom layer and the top layer, wherein the bottom layer is connected to a bottom layer contact portion of the first set of conductive paths and the top layer is connected to a top layer contact portion of the second or third set of conductive paths. The device further includes a multi-level via extending through the second dielectric layer and the third dielectric layer, between a first via contact portion of the first set of conductive paths and a second via contact portion of the third set of conductive paths, wherein a height of the MTJ device corresponds to, or is less than, a height of the multi-level via.
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