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公开(公告)号：US20250052857A1
公开(公告)日：2025-02-13
申请号：US18776961
申请日：2024-07-18
Applicant: Infineon Technologies AG
Inventor： Christoph Jürgen Will , Alexander Glas
IPC: G01S7/02 , G01S7/282 , G01S13/522
Abstract: In accordance with an embodiment, a method includes: obtaining a random delay for an emission of a radar pulse; and controlling a radar sensor to emit the radar pulse at a point in time delayed by the random delay.
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2.发明申请Integrated Circuits with Magnetic Core Inductors and Methods of Fabrications Thereof 审中-公开具有磁芯电感器的集成电路及其制造方法公开(公告)号：US20140203399A1
公开(公告)日：2014-07-24
申请号：US14219944
申请日：2014-03-19
Applicant: Infineon Technologies AG
Inventor： Renate Hofmann , Carsten Ahrens , Wolfgang Klein , Alexander Glas
CPC classification number: H01L28/10 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L25/16 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.
Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底之内和/或之上形成第一电感线圈。 第一电感线圈形成在衬底的顶侧附近。 第一沟槽形成在与第一电感线圈相邻的衬底内。 至少部分地用磁性填充材料填充第一沟槽。 至少第一电感线圈下面的衬底的第一部分变薄。 背面磁性层形成在基板的第一部分之下。 背面磁性层和磁性填充材料形成第一电感线圈的磁芯区域的至少一部分。
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3.发明授权Integrated circuits with magnetic core inductors and methods of fabrications thereof 有权具有磁芯电感器的集成电路及其制造方法公开(公告)号：US08709831B2
公开(公告)日：2014-04-29
申请号：US13903935
申请日：2013-05-28
Applicant: Infineon Technologies Ag
Inventor： Renate Hofmann , Carsten Ahrens , Wolfgang Klein , Alexander Glas
IPC: H01L27/22
CPC classification number: H01L28/10 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L25/16 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.
Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底之内和/或之上形成第一电感线圈。 第一电感线圈形成在衬底的顶侧附近。 第一沟槽形成在与第一电感线圈相邻的衬底内。 至少部分地用磁性填充材料填充第一沟槽。 至少第一电感线圈下面的衬底的第一部分变薄。 背面磁性层形成在基板的第一部分之下。 背面磁性层和磁性填充材料形成第一电感线圈的磁芯区域的至少一部分。
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公开(公告)号：US09577852B2
公开(公告)日：2017-02-21
申请号：US14531343
申请日：2014-11-03
Applicant: Infineon Technologies AG
Inventor： Maciej Wojnowski , Alexander Glas , Hubert Werthmann , Josef-Paul Schaffer , Francesca Arcioni , Gabriele Bettineschi
CPC classification number: H04L25/085 , H02H9/046 , H04L25/0276
Abstract: A common-mode suppressor for eliminating common-mode noise in high frequency differential data transmission systems and an associated method includes a long coiled differential transmission line configured to transfer data between a source and a load. The differential transmission line comprises a first conductive wire and a second conductive wire which are inductively and capacitively coupled and are laterally aligned or vertically aligned with each other. Further, the differential transmission line is matched for differential signals and un-matched for common-mode noise.
Abstract translation: 用于消除高频差分数据传输系统中的共模噪声的共模抑制器及相关方法包括：构造成在源和负载之间传送数据的长线圈差动传输线。 差分传输线包括电感和电容耦合并且彼此横向对准或垂直对准的第一导线和第二导线。 此外，差分传输线被匹配用于差分信号，并且对于共模噪声是不匹配的。
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公开(公告)号：US20140097514A1
公开(公告)日：2014-04-10
申请号：US13647740
申请日：2012-10-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Klaus Elian , Jens Pohl , Horst Theuss , Renate Hofmann , Alexander Glas , Carsten Ahrens
CPC classification number: H01L23/295 , H01F2017/0066 , H01F2017/0086 , H01L21/568 , H01L23/49816 , H01L23/5227 , H01L23/5389 , H01L23/645 , H01L24/19 , H01L24/96 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/73267 , H01L2224/94 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/12042 , H01L2924/1421 , H01L2924/1431 , H01L2924/1461 , H01L2924/181 , H01L2924/19042 , H01L2924/19104 , H01L2224/03 , H01L2924/00
Abstract: A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.
Abstract translation: 半导体封装包括半导体芯片，施加到半导体芯片的电感器。 电感器包括至少一个绕组。 至少一个绕组内的空间填充有磁性材料。
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Patent Agency Ranking
公开(公告)号：US09601920B2
公开(公告)日：2017-03-21
申请号：US14328573
申请日：2014-07-10
Applicant: Infineon Technologies AG
Inventor： Alexander Glas , Klaus Scharnagl
CPC classification number: H02H9/04 , H01L27/0248 , H01L27/0255 , H02H9/046
Abstract: According to an embodiment, a transient voltage protection circuit includes a first integrated circuit including an input node, an output node, a first transient voltage protection component coupled between the input node and a reference voltage node, and an impedance element coupled between the input node and the output node. The first transient voltage protection component has a first dynamic resistance and the output node is configured to be coupled to an electrostatic discharge (ESD) protection component having a second dynamic resistance that is greater than the first dynamic resistance.
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公开(公告)号：US20160127157A1
公开(公告)日：2016-05-05
申请号：US14531343
申请日：2014-11-03
Applicant: Infineon Technologies AG
Inventor： Maciej Wojnowski , Alexander Glas , Hubert Werthmann , Josef-Paul Schaffer , Francesca Arcioni , Gabriele Bettineschi
CPC classification number: H04L25/085 , H02H9/046 , H04L25/0276
Abstract: A common-mode suppressor for eliminating common-mode noise in high frequency differential data transmission systems and an associated method includes a long coiled differential transmission line configured to transfer data between a source and a load. The differential transmission line comprises a first conductive wire and a second conductive wire which are inductively and capacitively coupled and are laterally aligned or vertically aligned with each other. Further, the differential transmission line is matched for differential signals and un-matched for common-mode noise.
Abstract translation: 用于消除高频差分数据传输系统中的共模噪声的共模抑制器及相关方法包括：构造成在源和负载之间传送数据的长线圈差动传输线。 差分传输线包括电感和电容耦合并且彼此横向对准或垂直对准的第一导线和第二导线。 此外，差分传输线被匹配用于差分信号，并且对于共模噪声是不匹配的。
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8.发明授权Integrated circuits with magnetic core inductors and methods of fabrications thereof 有权具有磁芯电感器的集成电路及其制造方法公开(公告)号：US08975612B2
公开(公告)日：2015-03-10
申请号：US14219944
申请日：2014-03-19
Applicant: Infineon Technologies AG
Inventor： Renate Hofmann , Carsten Ahrens , Wolfgang Klein , Alexander Glas
CPC classification number: H01L28/10 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L25/16 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.
Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底之内和/或之上形成第一电感线圈。 第一电感线圈形成在衬底的顶侧附近。 第一沟槽形成在与第一电感线圈相邻的衬底内。 至少部分地用磁性填充材料填充第一沟槽。 至少第一电感线圈下面的衬底的第一部分变薄。 背面磁性层形成在基板的第一部分之下。 背面磁性层和磁性填充材料形成第一电感线圈的磁芯区域的至少一部分。
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公开(公告)号：US08952489B2
公开(公告)日：2015-02-10
申请号：US13647740
申请日：2012-10-09
Applicant: Infineon Technologies AG
Inventor： Klaus Elian , Jens Pohl , Horst Theuss , Renate Hofmann , Alexander Glas , Carsten Ahrens
IPC: H01L21/56 , H01L23/498 , H01L23/495 , H01L23/522 , H01L23/29
CPC classification number: H01L23/295 , H01F2017/0066 , H01F2017/0086 , H01L21/568 , H01L23/49816 , H01L23/5227 , H01L23/5389 , H01L23/645 , H01L24/19 , H01L24/96 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/73267 , H01L2224/94 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/12042 , H01L2924/1421 , H01L2924/1431 , H01L2924/1461 , H01L2924/181 , H01L2924/19042 , H01L2924/19104 , H01L2224/03 , H01L2924/00
Abstract: A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.
Abstract translation: 半导体封装包括半导体芯片，施加到半导体芯片的电感器。 电感器包括至少一个绕组。 至少一个绕组内的空间填充有磁性材料。
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10.发明申请Integrated Circuits With Magnetic Core Inductors And Methods of Fabrications Thereof 有权具有磁芯电感器的集成电路及其制造方法公开(公告)号：US20130260483A1
公开(公告)日：2013-10-03
申请号：US13903935
申请日：2013-05-28
Applicant: Infineon Technologies AG
Inventor： Renate Hofmann , Carsten Ahrens , Wolfgang Klein , Alexander Glas
IPC: H01L49/02
CPC classification number: H01L28/10 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01L23/5227 , H01L25/16 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.
Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底之内和/或之上形成第一电感线圈。 第一电感线圈形成在衬底的顶侧附近。 第一沟槽形成在与第一电感线圈相邻的衬底内。 至少部分地用磁性填充材料填充第一沟槽。 至少第一电感线圈下面的衬底的第一部分变薄。 背面磁性层形成在基板的第一部分之下。 背面磁性层和磁性填充材料形成第一电感线圈的磁芯区域的至少一部分。
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