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1.发明申请公开(公告)号：US20220085070A1
公开(公告)日：2022-03-17
申请号：US17423082
申请日：2019-11-04
发明人： Huaxiang YIN , Zhaozhao HOU , Tianchun YE , Chaolei LI
IPC分类号： H01L27/11597 , H01L21/28 , H01L29/51 , H01L27/1159
摘要： Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
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公开(公告)号：US20200328309A1
公开(公告)日：2020-10-15
申请号：US16720231
申请日：2019-12-19
发明人： Huaxiang YIN , Qingzhu ZHANG , Zhaohao ZHANG , Tianchun YE
摘要： A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1≤x≤0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
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公开(公告)号：US20240220355A1
公开(公告)日：2024-07-04
申请号：US18553929
申请日：2021-04-08
发明人： Qianhui LI , Qi WANG , Liu YANG , Yiyang JIANG , Xiaolei YU , Jing HE , Zongliang HUO , Tianchun YE
IPC分类号： G06F11/10
CPC分类号： G06F11/1008
摘要： A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.
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公开(公告)号：US20220231144A1
公开(公告)日：2022-07-21
申请号：US17214042
申请日：2021-03-26
发明人： Jun LUO , Tianchun YE , Dan ZHANG
IPC分类号： H01L29/423 , H01L29/417 , H01L29/40 , H01L29/06 , H01L29/786 , H01L29/66
摘要： A semiconductor structure, a method for manufacturing the semiconductor structure, and a transistor. A doped structure is provided, where the doped structure includes a dopant. A surface of the doped structure is oxidized to form the oxide film. In such case, the dopant at an interface between the oxide film and the doped structure may be redistributed, and thereby a segregated-dopant layer is formed inside or at a surface of the doped structure under the oxide film. A concentration of the dopant is higher in the segregated-dopant layer than in other regions of the doped structure. After the oxide film is removed, the doped structure with a high surface doping concentration can be obtained without an additional doping process. Therefore, after a conducting structure is formed on the segregated-dopant layer, a low contact resistance between the conducting structure and the doped structure is obtained, and a device performance is improved.
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公开(公告)号：US20180248022A1
公开(公告)日：2018-08-30
申请号：US15757601
申请日：2015-11-23
发明人： Tianchun YE
IPC分类号： H01L29/66 , H01L27/11582 , H01L21/02
CPC分类号： H01L29/66833 , H01L21/02172 , H01L21/02244 , H01L21/0228 , H01L21/02595 , H01L21/02667 , H01L27/1157 , H01L27/11582 , H01L29/66545
摘要： A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer comprises a barrier layer, a storage layer, a first interface layer, a tunneling layer, a second interface layer. In accordance with the semiconductor device and the manufacturing method of the present invention, an interface layer is added between the storage layer and tunneling layer in the gate dielectric by adjusting process step, and the peak concentration and peak location of nitrogen can be flexibly adjusted, effectively improving the quality of the interface between the storage layer and the tunneling layer in the gate dielectric layer, increasing process flexibility, improving device reliability and current characteristics.
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6.发明公开公开(公告)号：US20240365534A1
公开(公告)日：2024-10-31
申请号：US18630435
申请日：2024-04-09
发明人： Huilong ZHU , Tianchun YE , Jun LUO
CPC分类号： H10B12/482 , H10B12/05 , H10B12/485 , H10B12/488 , H10B61/22 , H10N50/10
摘要： A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.
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公开(公告)号：US20220254702A1
公开(公告)日：2022-08-11
申请号：US17666790
申请日：2022-02-08
发明人： Huilong ZHU , Tianchun YE
摘要： A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.
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公开(公告)号：US20200335596A1
公开(公告)日：2020-10-22
申请号：US16561192
申请日：2019-09-05
发明人： Huaxiang YIN , Jiaxin YAO , Qingzhu ZHANG , Zhaohao ZHANG , Tianchun YE
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L29/40 , H01L21/225
摘要： A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
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公开(公告)号：US20180261625A1
公开(公告)日：2018-09-13
申请号：US15758292
申请日：2015-11-23
发明人： Zongliang HUO , Tianchun YE
IPC分类号： H01L27/11582 , H01L21/308 , H01L21/306 , H01L21/762 , H01L21/02 , H01L21/027 , H01L21/311 , H01L29/10 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/02636 , H01L21/0274 , H01L21/30604 , H01L21/308 , H01L21/31111 , H01L21/762 , H01L21/76224 , H01L29/1037 , H01L29/40117 , H01L29/66545 , H01L29/66833 , H01L29/7926
摘要： A three-dimensional memory device and method of manufacturing the same, an isolation structure is embedded between the common source region and the substrate thereunder, which can inhibit the undesired diffusion of impurities during the implantation of the common source region, avoiding operation failure due to excessive diffusion of impurities. In programming and reading states of the three-dimensional memory device, electrons flow from the common source region to bit line; while in erase states, holes are injected from the substrate. Due to the isolation structure, the three-dimensional memory device achieves spatial separation of electrons from holes required for programming/erasing, improving the erasing efficiency and the integration as well.
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