公开(公告)号：US20220157820A1

公开(公告)日：2022-05-19

申请号：US17588938

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20200251160A1

公开(公告)日：2020-08-06

申请号：US16641574

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  PRASHANT MAJHI

IPC: G11C11/4096 ,  H01L27/108

Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

公开(公告)号：US20210288108A1

公开(公告)日：2021-09-16

申请号：US16326896

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  SHRIRAM SHIVARAMAN

IPC: H01L27/24 ,  H01L45/00

Abstract: Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector coupled to a storage cell. The storage cell may be a PCRAM storage cell, a MRAM storage cell, or a RRAM storage cell. In addition, a RRAM device may include a RRAM storage cell, coupled to a threshold switching selector, where the threshold switching selector may include a threshold switching layer and a semiconductor layer, and the semiconductor layer of the threshold switching selector may be shared with the semiconductor layer of the RRAM storage cell.

公开(公告)号：US20200007135A1

公开(公告)日：2020-01-02

申请号：US16024052

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： ABHISHEK A. SHARMA ,  RAVI PILLARISETTY ,  CHARLES KUO ,  WILLY RACHMADY

IPC: H03M1/00 ,  H03M1/74

Abstract: Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

公开(公告)号：US20210384419A1

公开(公告)日：2021-12-09

申请号：US16322890

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  SHRIRAM SHIVARAMAN

IPC: H01L45/00 ,  H01L27/24

Abstract: Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM storage cell may be coupled with a transistor to form a RRAM memory cell. The RRAM memory cell may include a semiconductor layer as a channel for the transistor, and also shared with the storage cell as an OEL for the storage cell. A shared electrode may serve as a source electrode of the transistor and an electrode of the storage cell. In some embodiments, a dielectric layer may be shared between the transistor and the storage cell, where the dielectric layer is a resistive switching material layer of the storage cell.

公开(公告)号：US20200152635A1

公开(公告)日：2020-05-14

申请号：US16473592

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/45

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20190198675A1

公开(公告)日：2019-06-27

申请号：US16329044

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  YIH WANG ,  SHRIRAM SHIVARAMAN

IPC: H01L29/786 ,  H01L21/768 ,  H01L23/50 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/50 ,  H01L29/66742 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.