公开(公告)号：US20170092846A1

公开(公告)日：2017-03-30

申请号：US15126682

申请日：2014-07-07

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  CHARLES C. KUO ,  MARK L. DOCZY ,  SATYARTH SURI ,  DAVID L. KENCKE ,  ROBERT S. CHAU ,  ROKSANA GOLIZADEH MOJARAD

IPC: H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C2213/52 ,  H01L27/222 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20160359101A1

公开(公告)日：2016-12-08

申请号：US15117605

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： CHARLES C. KUO ,  KAAN OGUZ ,  BRIAN S. DOYLE ,  MARK L. DOCZY ,  DAVID L. KENCKE ,  SATYARTH SURI ,  ROBERT S. CHAU

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

Abstract translation: 公开了用于制造具有点接触自由磁性层的自对准自旋转移转矩存储器（STTM）装置的技术。 在一些实施例中，所公开的STTM装置包括覆盖导电硬掩模层的侧壁的第一介电间隔物，其被图案化以提供用于STTM自由磁性层的电子接触。 硬掩模接触可以比自由磁性层更窄。 第一介电间隔物可用于图案化STTM的固定磁性层。 在一些实施例中，STTM还包括覆盖其自由磁性层的侧壁的任选的第二电介质间隔物。 第二电介质间隔物可以用于图案化STTM的固定磁性层，并且可以至少部分地用于保护自由磁性层的侧壁在这种图案化期间重新沉积蚀刻副产物，从而防止固定磁性层 和自由磁性层。

公开(公告)号：US20200251160A1

公开(公告)日：2020-08-06

申请号：US16641574

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  PRASHANT MAJHI

IPC: G11C11/4096 ,  H01L27/108

Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

公开(公告)号：US20190109281A1

公开(公告)日：2019-04-11

申请号：US16214306

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  CHARLES C. KUO ,  MARK L. DOCZY ,  SATYARTH SURI ,  DAVID L. KENCKE ,  ROBERT S. CHAU ,  ROKSANA GOLIZADEH MOJARAD

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C2213/52 ,  H01L27/222 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20160359108A1

公开(公告)日：2016-12-08

申请号：US15117594

申请日：2014-03-25

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  UDAY SHAH ,  NILOY MUKHERJEE ,  CHARLES C. KUO ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  ROBERT S. CHAU

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

Abstract translation: 公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。 该技术可以用于相对于给定存储器单元空间的平面电阻存储器单元来减少所形成的电压要求和/或电阻（例如在低电阻状态期间的电阻）。 非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。 在形成非平面电阻式存储单元之后，第二电极可以基本上位于开关层的相对部分之间，并且第一电极可以基本上与开关层的至少两侧相邻。 在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

公开(公告)号：US20210296040A1

公开(公告)日：2021-09-23

申请号：US16329309

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： KAAN OGUZ ,  KEVIN P. O'BRIEN ,  BRIAN S. DOYLE ,  CHARLES C. KUO ,  MARK L. DOCZY

IPC: H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.

公开(公告)号：US20180240969A1

公开(公告)日：2018-08-23

申请号：US15753478

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： MARK L. DOCZY ,  BRIAN S. DOYLE ,  CHARLES C. KUO ,  KAAN OGUZ ,  KEVIN P. O'BRIEN ,  SATYARTH SURI ,  TEJASWI K. INDUKURI

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20160126452A1

公开(公告)日：2016-05-05

申请号：US14992601

申请日：2016-01-11

Applicant: INTEL CORPORATION

Inventor： CHARLES C. KUO ,  BRIAN S. DOYLE ,  Arijit Raychowdhury ,  ROKSANA GOLIZADEH MOJARAD ,  KAAN OGUZ

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer.

Abstract translation: 公开了通过在其中实现附加铁磁层来增强垂直磁隧道结（MTJ）的性能的技术。 附加铁磁层可以例如在垂直MTJ的固定铁磁层或自由铁磁层中或以其它方式实现。 在一些实施例中，附加铁磁层用非磁性间隔件实现，其中可以调整附加铁磁层和/或间隔物的厚度以使垂直MTJ的平行和反平行状态之间的能量势垒充分平衡。 在一些实施例中，附加铁磁层被配置为使得其磁化强度与固定铁磁层的磁化强度相反。

公开(公告)号：US20190386014A1

公开(公告)日：2019-12-19

申请号：US16465044

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  RICKY J. TSENG ,  KEVIN P. O'BRIEN

IPC: H01L27/1159 ,  G11C5/06 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.

公开(公告)号：US20190198567A1

公开(公告)日：2019-06-27

申请号：US16328533

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. OBrien ,  BRIAN S. DOYLE ,  CHARLES C. KUO ,  Mark L. Doczy

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack and a fixed magnetic stack separated by a dielectric tunneling layer. The free magnetic stack includes an uppermost magnetic layer that is at least partially covered by a cap layer. The cap layer is at least partially covered by a protective layer containing at least one of: ruthenium (Ru); cobalt/iron/boron (CoFeB); molybdenum (Mo); cobalt (Co); tungsten (W); or platinum (Pt). The protective layer is at least partially covered by a cap metal layer which may form a portion of MTJ electrode. The protective layer minimizes the occurrence of physical and/or chemical attack of the cap layer by the materials used in the cap metal layer, beneficially improving the interface anisotropy of the