公开(公告)号：US20180374928A1

公开(公告)日：2018-12-27

申请号：US15776752

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  ASHISH AGRAWAL ,  BENJAMIN CHU-KUNG ,  VAN H. LE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  RAFAEL RIOS

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/513 ,  H01L29/16 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210384419A1

公开(公告)日：2021-12-09

申请号：US16322890

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  SHRIRAM SHIVARAMAN

IPC: H01L45/00 ,  H01L27/24

Abstract: Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM storage cell may be coupled with a transistor to form a RRAM memory cell. The RRAM memory cell may include a semiconductor layer as a channel for the transistor, and also shared with the storage cell as an OEL for the storage cell. A shared electrode may serve as a source electrode of the transistor and an electrode of the storage cell. In some embodiments, a dielectric layer may be shared between the transistor and the storage cell, where the dielectric layer is a resistive switching material layer of the storage cell.

公开(公告)号：US20190198675A1

公开(公告)日：2019-06-27

申请号：US16329044

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  YIH WANG ,  SHRIRAM SHIVARAMAN

IPC: H01L29/786 ,  H01L21/768 ,  H01L23/50 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/50 ,  H01L29/66742 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.

公开(公告)号：US20210288108A1

公开(公告)日：2021-09-16

申请号：US16326896

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  SHRIRAM SHIVARAMAN

IPC: H01L27/24 ,  H01L45/00

Abstract: Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector coupled to a storage cell. The storage cell may be a PCRAM storage cell, a MRAM storage cell, or a RRAM storage cell. In addition, a RRAM device may include a RRAM storage cell, coupled to a threshold switching selector, where the threshold switching selector may include a threshold switching layer and a semiconductor layer, and the semiconductor layer of the threshold switching selector may be shared with the semiconductor layer of the RRAM storage cell.

公开(公告)号：US20150021553A1

公开(公告)日：2015-01-22

申请号：US14507044

申请日：2014-10-06

Applicant: Intel Corporation

Inventor： ANNALISA CAPPELLANI ,  KELIN J. KUHN ,  RAFAEL RIOS ,  Titash Rakshit ,  Sivakumar Mudanai

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/775 ,  H01L29/0669 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Abstract translation: 无连接累积模式（JAM）半导体器件通过JAM半导体的突出特征之下的反向偏压带从半导体衬底隔离。 制造JAM器件的过程包括植入和外延。