公开(公告)号：US11036412B2

公开(公告)日：2021-06-15

申请号：US16585801

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Sahar Khalili ,  Zvika Greenfield ,  Sowmiya Jayachandran ,  Robert J. Royer, Jr. ,  Dimpesh Patel

IPC: G06F3/06 ,  G06F12/0862

Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.

公开(公告)号：US10956323B2

公开(公告)日：2021-03-23

申请号：US15976795

申请日：2018-05-10

Applicant: Intel Corporation

Inventor： Dale J. Juenemann ,  James A. Boyd ,  Robert J. Royer, Jr.

IPC: G06F12/08 ,  G06F12/0804 ,  G06F3/06

Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.

公开(公告)号：US10949356B2

公开(公告)日：2021-03-16

申请号：US16442267

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： James A. Boyd ,  Robert J. Royer, Jr. ,  Lily P. Looi ,  Gary C. Chow ,  Zvika Greenfield ,  Chia-Hung S. Kuo ,  Dale J. Juenemann

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.

公开(公告)号：US10540505B2

公开(公告)日：2020-01-21

申请号：US15721554

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： James A. Boyd ,  Dale J. Juenemann ,  Robert J. Royer, Jr.

IPC: G06F11/30 ,  G06F21/60 ,  G06F3/06 ,  G06F16/27

Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.

公开(公告)号：US10402565B2

公开(公告)日：2019-09-03

申请号：US15419368

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Nitin V. Sarangdhar ,  Robert J. Royer, Jr. ,  Eng Hun Ooi ,  Brian R. McFarlane ,  Mukesh Kataria

IPC: G06F21/57 ,  G06F9/44 ,  G06F11/14 ,  G06F9/4401

Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.

公开(公告)号：US10304814B2

公开(公告)日：2019-05-28

申请号：US15640148

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Konika Ganguly ,  Robert J. Royer, Jr. ,  Rebecca Z. Loop ,  Anthony M. Constantine ,  Bilal Khalaf

IPC: G11C14/00 ,  H01L23/50 ,  H01L25/18 ,  H01L23/498

Abstract: An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.

公开(公告)号：US10248343B2

公开(公告)日：2019-04-02

申请号：US15357783

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： Jason B. Akers ,  Knut S. Grimsrud ,  Robert J. Royer, Jr. ,  Richard P. Mangold ,  Sanjeev N. Trika

IPC: G11C14/00 ,  G06F3/06 ,  G11C5/14 ,  G06F1/3287 ,  G11C7/10 ,  G06F11/14

Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

公开(公告)号：US12248356B2

公开(公告)日：2025-03-11

申请号：US17359403

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Virendra Vikramsinh Adsure ,  Chia-Hung S. Kuo ,  Robert J. Royer, Jr. ,  Deepak Gandiga Shivakumar

IPC: G06F1/3293

Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.

公开(公告)号：US10296217B2

公开(公告)日：2019-05-21

申请号：US15618170

申请日：2017-06-09

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Mark A. Schmisseur ,  Raymond S. Tetrick ,  Robert J. Royer, Jr. ,  David B. Minturn ,  Shane Matthews

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

公开(公告)号：US20160034345A1

公开(公告)日：2016-02-04

申请号：US14775848

申请日：2014-02-26

Applicant: Robert J. ROYER, JR. ,  Blaise FANNING ,  Eng Hun OOI ,  INTEL CORPORATION

Inventor： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了用于管理存储器延迟操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控​​制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，以及实现数据管理策略 响应于纠错码指示器。 还公开并要求保护其他实施例。