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    TECHNIQUES TO PROVIDE HARDWARE ENFORCED PROTECTION ENVIRONMENT FOR A SYSTEM MANAGEMENT MODE
    2.
    发明申请
    TECHNIQUES TO PROVIDE HARDWARE ENFORCED PROTECTION ENVIRONMENT FOR A SYSTEM MANAGEMENT MODE 审中-公开

    公开(公告)号：US20190042780A1

    公开(公告)日：2019-02-07

    申请号：US15941992

    申请日：2018-03-30

    Applicant: INTEL CORPORATION

    Inventor： KIRK D. BRANNOCK ,  BARRY E. HUNTLEY

    IPC: G06F21/62 ,  G06F21/64

    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to detect an access request to access a computing resource while in a system management mode (SMM), determine a bit of a lock register is set to enable access to a bitmap associated with the computing resource, the bitmap to indicate an access policy for the computing resource, and determine whether the access request violate the access policy set in the bitmap. Embodiments may also include performing the access request if the access request does not violate the access policy, and causing a fault if the access request does violate the access policy.

    METHOD AND APPARATUS FOR LIGHT-WEIGHT VIRTUALIZATION CONTEXTS
    3.
    发明申请
    METHOD AND APPARATUS FOR LIGHT-WEIGHT VIRTUALIZATION CONTEXTS 有权

    公开(公告)号：US20170090966A1

    公开(公告)日：2017-03-30

    申请号：US14867761

    申请日：2015-09-28

    Applicant: Intel Corporation

    Inventor： DEEPAK K. GUPTA ,  RAVI L. SAHITA ,  BARRY E. HUNTLEY

    IPC: G06F9/455

    CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45575

    Abstract: A processor comprises a register to store a first pointer to a context data structure specifying a virtual machine context, the context data structure comprising a first field to store a second pointer to a plurality of realm switch control structures (RSCSs), and an execution unit comprising a logic circuit to execute a virtual machine (VM) according to the virtual machine context, wherein the VM comprises a guest operating system (OS) comprising a plurality of kernel components, and wherein each RSCS of the plurality of RSCSs specifies a respective component context associated with a respective kernel component of the plurality of kernel components, and execute a first kernel component of the plurality of kernel components using a first component context specified by a first RSCS of the plurality of RSCSs.

    INSTRUCTIONS AND LOGIC TO PROVIDE ADVANCED PAGING CAPABILITIES FOR SECURE ENCLAVE PAGE CACHES
    4.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE ADVANCED PAGING CAPABILITIES FOR SECURE ENCLAVE PAGE CACHES 审中-公开
    指示和逻辑提供先进的分页功能，以确保安全的页面缓存

    公开(公告)号：US20160371191A1

    公开(公告)日：2016-12-22

    申请号：US15250787

    申请日：2016-08-29

    Applicant: Intel Corporation

    Inventor： CARLOS V. ROZAS ,  ILYA ALEXANDROVICH ,  ITTAI ANATI ,  ALEX BERENZON ,  MICHAEL A. GOLDSMITH ,  BARRY E. HUNTLEY ,  ANTON IVANOV ,  SIMON P. JOHNSON ,  REBEKAH M. LESLIE-HURD ,  FRANCIS X. MCKEEN ,  GILBERT NEIGER ,  RINAT RAPPOPORT ,  SCOTT D. RODGERS ,  UDAY R. SAVAGAONKAR ,  VINCENT R. SCARLATA ,  VEDVYAS SHANBHOGUE ,  WESLEY H. SMITH ,  WILLIAM C. WOOD

    IPC: G06F12/0875 ,  G06F12/1027

    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

    Abstract translation: 说明和逻辑为安全的飞地页面缓存提供了高级分页功能。 实施例包括多个硬件线程或处理核心，用于存储分配给由硬件线程可访问的安全空间的共享页面地址的安全数据的高速缓存。 解码级将指定所述共享页地址的第一指令解码为操作数，并且执行单元标记对应于共享页地址的飞地页高速缓存映射的条目，以阻止所述第一或第二硬件线程中的任一个的新转换的创建 访问共享页面。 第二指令被解码以执行，第二指令指定所述安全飞地作为操作数，并且执行单元记录当前访问与安全飞地相对应的飞地页面高速缓存中的安全数据的硬件线程，并且当任何 的硬件线程退出安全飞地。

    PROTECTING CONFIDENTIAL DATA WITH TRANSACTIONAL PROCESSING IN EXECUTE-ONLY MEMORY
    6.
    发明申请
    PROTECTING CONFIDENTIAL DATA WITH TRANSACTIONAL PROCESSING IN EXECUTE-ONLY MEMORY 有权
    通过实时处理保护机密数据

    公开(公告)号：US20160378490A1

    公开(公告)日：2016-12-29

    申请号：US14752079

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： MICHAEL LEMAY ,  DAVID M. DURHAM ,  BARRY E. HUNTLEY ,  VEDVYAS SHANBHOGUE ,  RAVI L. SAHITA ,  RAVI RAJWAR

    IPC: G06F9/38 ,  G06F11/07

    CPC classification number: G06F9/3802 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/46 ,  G06F11/0745 ,  G06F11/0751

    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for protecting confidential data with transactional processing in execute-only memory. The system may include a memory module configured to store an execute-only code page. The system may also include a transaction processor configured to enforce a transaction region associated with at least a portion of the code page. The system may further include a processor configured to execute a load instruction fetched from the code page, the load instruction configured to load at least a portion of the confidential data from an immediate operand of the load instruction if a transaction mode of the transaction region is enabled.

    Abstract translation: 通常，本公开提供了用于在仅执行存储器中用事务处理保护机密数据的系统，设备，方法和计算机可读介质。 该系统可以包括被配置为存储仅执行代码页的存储器模块。 系统还可以包括配置成强制与代码页的至少一部分相关联的事务区域的事务处理器。 该系统还可以包括：处理器，其被配置为执行从代码页取出的加载指令，所述加载指令被配置为如果交易区域的交易模式是来自加载指令的即时操作数，则加载秘密数据的至少一部分 启用

    MEMORY MANAGEMENT APPARATUS AND METHOD FOR MANAGING DIFFERENT PAGE TABLES FOR DIFFERENT PRIVILEGE LEVELS
    8.
    发明申请
    MEMORY MANAGEMENT APPARATUS AND METHOD FOR MANAGING DIFFERENT PAGE TABLES FOR DIFFERENT PRIVILEGE LEVELS 审中-公开

    公开(公告)号：US20200310978A1

    公开(公告)日：2020-10-01

    申请号：US16367103

    申请日：2019-03-27

    Applicant: Intel Corporation

    Inventor： SCOTT DION RODGERS ,  ROBERT S. CHAPPELL ,  BARRY E. HUNTLEY

    IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

    Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

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