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    Architecture for on-die interconnect
    7.
    发明授权
    Architecture for on-die interconnect 有权
    管芯互连架构

    公开(公告)号：US09287208B1

    公开(公告)日：2016-03-15

    申请号：US14524622

    申请日：2014-10-27

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Ankit More ,  Dinesh Somasekhar ,  David S. Dunning

    IPC: H01L25/00 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H04L49/109 ,  H01L23/5221 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种装置包括：配置在半导体管芯上的多个岛，多个岛中的每一个具有多个核; 以及多个网络交换机，其配置在所述半导体管芯上并且各自与所述多个岛中的一个岛相关联，其中每个网络交换机包括多个输出端口，所述输出端口的第一组各自耦合到相关联的网络交换机 经由点对点互连的岛屿和第二组输出端口各自经由点对多点互连耦合到多个岛的相关网络交换机。 描述和要求保护其他实施例。

    Optoelectronic transceiver with power management
    8.
    发明授权
    Optoelectronic transceiver with power management 有权

    公开(公告)号：US10171168B2

    公开(公告)日：2019-01-01

    申请号：US15081784

    申请日：2016-03-25

    Applicant: Intel Corporation

    Inventor： Rohit Mittal ,  David S. Dunning

    IPC: H04B10/516 ,  H04B10/40 ,  H04B10/69 ,  H04B10/50 ,  H04B10/564 ,  H04L7/00

    Abstract: Embodiments herein relate to optoelectronic transceivers with power management. An optoelectronic device may include a photodetector, a loss of signal (LOS) detector coupled with the photodetector, and a re-timer coupled with the LOS detector, wherein a component of the re-timer is to be disabled in response to a detection by the LOS detector that an optical signal has not been received for a predetermined time period. In some embodiments, the LOS detector is coupled with a driver disable input of the re-timer and a driver component of the re-timer is to be disabled. In some embodiments, a clock data recovery circuit, a transmit module re-timer and modulator, and/or a laser may be disabled. In various embodiments, components may be re-enabled in response to detection that an optical signal is being received and/or an electrical signal is received for optical transmission. Other embodiments may be described and/or claimed.

    Architecture For On-Die Interconnect
    9.
    发明申请
    Architecture For On-Die Interconnect 审中-公开
    架构互连

    公开(公告)号：US20160173413A1

    公开(公告)日：2016-06-16

    申请号：US15042402

    申请日：2016-02-12

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Ankit More ,  Dinesh Somasekhar ,  David S. Dunning

    IPC: H04L12/933 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H04L49/109 ,  H01L23/5221 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种装置包括：配置在半导体管芯上的多个岛，多个岛中的每一个具有多个核; 以及多个网络交换机，其配置在所述半导体管芯上并且各自与所述多个岛中的一个岛相关联，其中每个网络交换机包括多个输出端口，所述输出端口的第一组各自耦合到相关联的网络交换机 经由点对点互连的岛屿和第二组输出端口各自经由点对多点互连耦合到多个岛的相关网络交换机。 描述和要求保护其他实施例。

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