公开(公告)号：US20170170153A1

公开(公告)日：2017-06-15

申请号：US14967231

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

IPC: H01L25/10 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  G06F1/12 ,  G06F13/4022 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5386 ,  H01L25/50 ,  H04L49/101

Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

公开(公告)号：US20170086271A1

公开(公告)日：2017-03-23

申请号：US15365484

申请日：2016-11-30

Applicant: Intel Corporation

Inventor： Shekhar Y. Borkar ,  Stephen G. Eichenlaub

IPC: H05B33/08 ,  H05B37/02

CPC classification number: H05B33/0815 ,  F21K9/232 ,  F21K9/233 ,  F21K9/235 ,  F21K9/238 ,  F21V3/02 ,  F21Y2101/00 ,  F21Y2113/13 ,  F21Y2115/10 ,  H05B33/0818 ,  H05B33/0845 ,  H05B33/0857 ,  H05B37/0245 ,  H05B37/0272 ,  Y02B20/19 ,  Y02B20/383

Abstract: In some embodiments, a light device for generating light includes light emitting diodes (LEDs), and power supply circuitry including at least one switching regulator including switching elements to provide power to the LEDs. The light device includes a device support structure including a device connector and an LED support to support the LEDs, wherein the device connector is one end of the device support structure, and the power supply circuitry is supported by the device support structure. Other embodiments are described.

公开(公告)号：US09837391B2

公开(公告)日：2017-12-05

申请号：US14967231

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

IPC: H01L23/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  G06F1/12 ,  H01L23/522 ,  H01L23/528 ,  G06F13/40 ,  H04L12/933

CPC classification number: H01L25/105 ,  G06F1/12 ,  G06F13/4022 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5386 ,  H01L25/50 ,  H04L49/101

Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

公开(公告)号：US09516712B2

公开(公告)日：2016-12-06

申请号：US14069283

申请日：2013-10-31

Applicant: Intel Corporation

Inventor： Shekhar Y. Borkar ,  Stephen G. Eichenlaub

IPC: H05B33/08 ,  H05B37/02 ,  F21Y101/00

CPC classification number: H05B33/0815 ,  F21K9/232 ,  F21K9/233 ,  F21K9/235 ,  F21K9/238 ,  F21V3/02 ,  F21Y2101/00 ,  F21Y2113/13 ,  F21Y2115/10 ,  H05B33/0818 ,  H05B33/0845 ,  H05B33/0857 ,  H05B37/0245 ,  H05B37/0272 ,  Y02B20/19 ,  Y02B20/383

Abstract: In some embodiments, a light device for generating light includes light emitting diodes (LEDs), and power supply circuitry including at least one switching regulator including switching elements to provide power to the LEDs. The light device includes a device support structure including a device connector and an LED support to support the LEDs, wherein the device connector is one end of the device support structure, and the power supply circuitry is supported by the device support structure. Other embodiments are described.

公开(公告)号：US20170171111A1

公开(公告)日：2017-06-15

申请号：US14967166

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Ankit More ,  David S. Dunning ,  Nitin Y. Borkar ,  Shekhar Y. Borkar

IPC: H04L12/935 ,  H04L12/721 ,  H04L12/933

CPC classification number: H04L49/30 ,  H04L49/101 ,  H04L49/109 ,  H04L49/253

Abstract: Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

公开(公告)号：USRE49439E1

公开(公告)日：2023-02-28

申请号：US16703812

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

IPC: H01L23/532 ,  H01L21/78

Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

公开(公告)号：US10021743B2

公开(公告)日：2018-07-10

申请号：US15365484

申请日：2016-11-30

Applicant: Intel Corporation

Inventor： Shekhar Y. Borkar ,  Stephen G. Eichenlaub

IPC: H05B37/02 ,  H05B33/08 ,  F21K9/232 ,  F21K9/233 ,  F21Y101/00 ,  F21Y115/10 ,  F21Y113/13 ,  F21K9/238 ,  F21K9/235 ,  F21V3/02

CPC classification number: H05B33/0815 ,  F21K9/232 ,  F21K9/233 ,  F21K9/235 ,  F21K9/238 ,  F21V3/02 ,  F21Y2101/00 ,  F21Y2113/13 ,  F21Y2115/10 ,  H05B33/0818 ,  H05B33/0845 ,  H05B33/0857 ,  H05B37/0245 ,  H05B37/0272 ,  Y02B20/19 ,  Y02B20/383

Abstract: In some embodiments, a light device for generating light includes light emitting diodes (LEDs), and power supply circuitry including at least one switching regulator including switching elements to provide power to the LEDs. The light device includes a device support structure including a device connector and an LED support to support the LEDs, wherein the device connector is one end of the device support structure, and the power supply circuitry is supported by the device support structure. Other embodiments are described.

公开(公告)号：US09992135B2

公开(公告)日：2018-06-05

申请号：US14967166

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Ankit More ,  David S. Dunning ,  Nitin Y. Borkar ,  Shekhar Y. Borkar

IPC: H04L12/28 ,  H04L12/935 ,  H04L12/933 ,  H04L12/721

CPC classification number: H04L49/30 ,  H04L49/101 ,  H04L49/109 ,  H04L49/253

Abstract: Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

公开(公告)号：US20230110247A1

公开(公告)日：2023-04-13

申请号：US17977236

申请日：2022-10-31

Applicant: Intel Corporation

Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

IPC: H01L23/532 ,  H01L21/78

Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

公开(公告)号：US20160170456A9

公开(公告)日：2016-06-16

申请号：US13626357

申请日：2012-09-25

Applicant: INTEL CORPORATION

Inventor： Siva G. Narendra ,  James W. Tschanz ,  Howard A. Wilson ,  Donald S. Gardner ,  Peter Hazucha ,  Gerhard Schrom ,  Tanay Karnik ,  Nitin Borkar ,  Vivek K. De ,  Shekhar Y. Borkar

IPC: G06F1/26 ,  G06F1/32 ,  H01L25/065

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  H01L23/34 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  Y02D10/126 ,  Y02D10/172

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract translation: 公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。