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    DATA MULTIPLEXER SINGLE PHASE FLIP-FLOP
    1.
    发明申请
    DATA MULTIPLEXER SINGLE PHASE FLIP-FLOP 有权

    公开(公告)号：US20220399893A1

    公开(公告)日：2022-12-15

    申请号：US17346034

    申请日：2021-06-11

    Applicant: Intel Corporation

    Inventor： Chinmay Joshi ,  Dinesh Somasekhar

    IPC: H03K19/0185 ,  H03K19/173 ,  H03K19/21 ,  H03K3/3562

    Abstract: A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.

    Fast search of error correction code (ECC) protected data in a memory
    2.
    发明授权
    Fast search of error correction code (ECC) protected data in a memory 有权

    公开(公告)号：US10884853B2

    公开(公告)日：2021-01-05

    申请号：US16249631

    申请日：2019-01-16

    Applicant: Intel Corporation

    Inventor： Wei Wu ,  Dinesh Somasekhar ,  Jon Stephan ,  Aravinda K. Radhakrishnan ,  Vivek Kozhikkottu

    IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

    Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.

    FAST SEARCH OF ERROR CORRECTION CODE (ECC) PROTECTED DATA IN A MEMORY
    5.
    发明申请
    FAST SEARCH OF ERROR CORRECTION CODE (ECC) PROTECTED DATA IN A MEMORY 审中-公开

    公开(公告)号：US20190146873A1

    公开(公告)日：2019-05-16

    申请号：US16249631

    申请日：2019-01-16

    Applicant: Intel Corporation

    Inventor： Wei Wu ,  Dinesh Somasekhar ,  Jon Stephan ,  Aravinda K. Radhakrishnan ,  Vivek Kozhikkottu

    IPC: G06F11/10 ,  G11C29/52

    Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.

    LOW LATENCY STATISTICAL DATA BUS INVERSION FOR ENERGY REDUCTION
    6.
    发明申请
    LOW LATENCY STATISTICAL DATA BUS INVERSION FOR ENERGY REDUCTION 审中-公开

    公开(公告)号：US20180285304A1

    公开(公告)日：2018-10-04

    申请号：US15475571

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Kon-Woo Kwon ,  Dinesh Somasekhar

    IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

    Scalable polylithic on-package integratable apparatus and method
    8.
    再颁专利
    Scalable polylithic on-package integratable apparatus and method 有权

    公开(公告)号：USRE49439E1

    公开(公告)日：2023-02-28

    申请号：US16703812

    申请日：2019-12-04

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

    IPC: H01L23/532 ,  H01L21/78

    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

    DEVICE, SYSTEM AND METHOD FOR MEMORY REPAIR WITH MULTI-CELL SWITCHING
    9.
    发明申请
    DEVICE, SYSTEM AND METHOD FOR MEMORY REPAIR WITH MULTI-CELL SWITCHING 有权

    公开(公告)号：US20210407618A1

    公开(公告)日：2021-12-30

    申请号：US16912498

    申请日：2020-06-25

    Applicant: Intel Corporation

    Inventor： Aravinda Radhakrishnan ,  Marcus Wing-Kin Cheung ,  Dinesh Somasekhar ,  Naga Mallika Bhandaru ,  Michael Nelms ,  Rodrigo Gonzalez Gutierrez ,  Kaitlyn Chen

    IPC: G11C29/00

    Abstract: Techniques and mechanisms for a memory device to support memory repair functionality for a column of a memory array. In an embodiment, the column comprises first memory cells and second memory cells, where switch circuitry is coupled between multiple signal lines and the column. Control circuitry transitions the switch circuitry to a state which corresponds to a defective one of the first cells. The state switchedly decouples the defective cell, and an adjoining one of the first cells, each from respective ones of the signal lines. During the state, two or more of the signal lines are able to communicate each to a different respective one of the second cells. In another embodiment, the switch circuitry is transitioned to the state based on an identifier of the defective cell, and independent of whether any other cell of the column has been identified as defective.

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