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    DUAL METAL GATE STRUCTURES ON NANORIBBON SEMICONDUCTOR DEVICES
    2.
    发明申请
    DUAL METAL GATE STRUCTURES ON NANORIBBON SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230062210A1

    公开(公告)日：2023-03-02

    申请号：US17460524

    申请日：2021-08-30

    Applicant: Intel Corporation

    Inventor： Andy Chih-Hung Wei ,  Yang-Chun Cheng ,  Dax M. Crum

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8234

    Abstract: Techniques are provided herein to form semiconductor devices having different work function metals over different devices. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to gate-all-around (GAA) transistors. In an example, neighboring semiconductor devices each include a different work function to act as the device gate electrode for each semiconductor device. More specifically, a first semiconductor device may be a p-channel GAA transistor with a first work function metal around the various nanoribbons of the transistor, while the second neighboring semiconductor device may be an n-channel GAA transistor with a second work function metal around the various nanoribbons of the transistor. No portions of the first work function metal are present around the nanoribbons of the second semiconductor device and no portions of the second work function metal are present around the nanoribbons of the first semiconductor device.

    Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
    4.
    发明授权
    Self-aligned gate endcap (SAGE) architectures with gate-all-around devices 有权

    公开(公告)号：US11233152B2

    公开(公告)日：2022-01-25

    申请号：US16017966

    申请日：2018-06-25

    Applicant: Intel Corporation

    Inventor： Biswajeet Guha ,  William Hsu ,  Leonard P. Guler ,  Dax M. Crum ,  Tahir Ghani

    IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

    Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
    5.
    发明授权
    Self-aligned gate endcap (SAGE) architectures with gate-all-around devices 有权

    公开(公告)号：US12224350B2

    公开(公告)日：2025-02-11

    申请号：US18374959

    申请日：2023-09-29

    Applicant: Intel Corporation

    Inventor： Biswajeet Guha ,  William Hsu ,  Leonard P. Guler ,  Dax M. Crum ,  Tahir Ghani

    IPC: H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

    Increased transistor source/drain contact area using sacrificial source/drain layer
    7.
    发明授权
    Increased transistor source/drain contact area using sacrificial source/drain layer 有权

    公开(公告)号：US11495672B2

    公开(公告)日：2022-11-08

    申请号：US16023024

    申请日：2018-06-29

    Applicant: INTEL CORPORATION

    Inventor： Dax M. Crum ,  Biswajeet Guha ,  William Hsu ,  Stephen M. Cea ,  Tahir Ghani

    IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

    Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.

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