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公开(公告)号:US10483249B2
公开(公告)日:2019-11-19
申请号:US16060658
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Donald S. Gardner , Edward A. Burton , Gerhard Schrom , Larry E. Mosley
Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.
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公开(公告)号:US20180232041A1
公开(公告)日:2018-08-16
申请号:US15951310
申请日:2018-04-12
Applicant: Intel Corporation
Inventor: Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
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公开(公告)号:US20180232040A1
公开(公告)日:2018-08-16
申请号:US15951299
申请日:2018-04-12
Applicant: Intel Corporation
Inventor: Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
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公开(公告)号:US20210043620A1
公开(公告)日:2021-02-11
申请号:US17069517
申请日:2020-10-13
Applicant: Intel Corporation
Inventor: Edward A. Burton
IPC: H01L25/18 , H01L23/538 , H01L23/31 , H01L25/00
Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.
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公开(公告)号:US20200066651A1
公开(公告)日:2020-02-27
申请号:US16611129
申请日:2017-06-29
Applicant: INTEL CORPORATION
Inventor: Edward A. Burton , Mark T. Bohr , Murray Fitzpatrick Kelley , Shawn Michael Klauser
IPC: H01L23/544 , H01L23/538 , G03F7/20
Abstract: Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.
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公开(公告)号:US10534419B2
公开(公告)日:2020-01-14
申请号:US15951310
申请日:2018-04-12
Applicant: Intel Corporation
Inventor: Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC: G06F1/32 , G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
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7.
公开(公告)号:US10319700B1
公开(公告)日:2019-06-11
申请号:US15859404
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Edward A. Burton
IPC: H01L23/66 , H01L25/065 , H01L23/367 , H01L23/373 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0652 , H01L23/3675 , H01L23/3736 , H01L23/3738 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/50 , H01L2224/32245 , H01L2224/73253 , H01L2225/06506 , H01L2225/06513 , H01L2225/06555 , H01L2225/06589
Abstract: Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.
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公开(公告)号:US10095300B2
公开(公告)日:2018-10-09
申请号:US15800144
申请日:2017-11-01
Applicant: Intel Corporation
Inventor: Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC: G06F1/32
Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
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公开(公告)号:US20150286265A1
公开(公告)日:2015-10-08
申请号:US14689175
申请日:2015-04-17
Applicant: Intel Corporation
Inventor: Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
Abstract translation: 两个或多个处理核心的独立功率控制。 更具体地,本发明的至少一个实施例涉及将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术。
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公开(公告)号:US11502071B2
公开(公告)日:2022-11-15
申请号:US17069517
申请日:2020-10-13
Applicant: Intel Corporation
Inventor: Edward A. Burton
IPC: H01L25/18 , H01L23/538 , H01L23/31 , H01L25/00
Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.
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