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    Dynamically controlling power management of an on-die memory of a processor
    1.
    发明授权
    Dynamically controlling power management of an on-die memory of a processor 有权

    公开(公告)号：US09684360B2

    公开(公告)日：2017-06-20

    申请号：US14528076

    申请日：2014-10-30

    Applicant: Intel Corporation

    Inventor： Eli Kupermann ,  Elena Agranovsky

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.

    TESTING OF DEVICE SENSORS ON A MANUFACTURING LINE
    3.
    发明申请
    TESTING OF DEVICE SENSORS ON A MANUFACTURING LINE 审中-公开

    公开(公告)号：US20170254683A1

    公开(公告)日：2017-09-07

    申请号：US15061535

    申请日：2016-03-04

    Applicant: Intel Corporation

    Inventor： Yael Yanai ,  Yehiel Shilo ,  Eli Kupermann ,  Chen-Hsun Wu ,  Elena Agranovsky ,  Marlon D. Bada

    IPC: G01D18/00

    Abstract: Embodiments of the present disclosure provide techniques for sensor testing for computing devices during initial movement of the device, such as movement on a manufacturing line. In one instance, a device with integral sensor testing during initial movement of the device may include a plurality of sensors and a sensor test block coupled with the plurality of sensors, to detect, collect and/or report readings provided by at least some of the sensors in response to movement of the device between at least a first test station and a second test station. Other embodiments may be described and/or claimed.

    Multi-mode protected memory
    4.
    发明授权
    Multi-mode protected memory 有权

    公开(公告)号：US11816039B2

    公开(公告)日：2023-11-14

    申请号：US17441214

    申请日：2019-04-19

    Applicant: Intel Corporation

    Inventor： Adrian Pearson ,  Bing Zhu ,  Elena Agranovsky ,  Tomas Winkler ,  Yang Huang

    IPC: G06F12/14

    CPC classification number: G06F12/1408 ,  G06F12/1425 ,  G06F12/1466

    Abstract: Multi-mode protected memory in accordance with the present description includes a permanent mode and a transient mode of operation. In one embodiment of the permanent mode, an authentication key is programmable once and a write counter is not decrementable or resettable. In one embodiment of the transient mode, an authentication key may be programmed many times and a write counter may be reset many times. Other features and advantages may be realized, depending upon the particular application.

    Dynamically Controlling Power Management Of An On-Die Memory Of A Processor
    5.
    发明申请
    Dynamically Controlling Power Management Of An On-Die Memory Of A Processor 有权
    动态控制处理器的片上存储器的电源管理

    公开(公告)号：US20160124490A1

    公开(公告)日：2016-05-05

    申请号：US14528076

    申请日：2014-10-30

    Applicant: Intel Corporation

    Inventor： Eli Kupermann ,  Elena Agranovsky

    IPC: G06F1/32 ,  G06F12/02

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括：执行指令的至少一个核; 耦合到所述至少一个核的存储器，所述存储器包括用于存储信息的多个页面; 以及耦合到所述存储器的页面管理器，所述页面管理器访问与所述存储器的页面相关联的页表条目的元数据，并更新数据库的条目的使用信息，与所述存储器的页面相关联的数据库的条目 。 页面管理器可以至少部分地基于使用信息使至少一部分内存被动态地关机。 描述和要求保护其他实施例。

    Testing of device sensors on a manufacturing line
    6.
    发明授权
    Testing of device sensors on a manufacturing line 有权

    公开(公告)号：US10677618B2

    公开(公告)日：2020-06-09

    申请号：US15061535

    申请日：2016-03-04

    Applicant: Intel Corporation

    Inventor： Yael Yanai ,  Yehiel Shilo ,  Eli Kupermann ,  Chen-Hsun Wu ,  Elena Agranovsky ,  Marlon D. Bada

    IPC: G01D18/00

    Abstract: Embodiments of the present disclosure provide techniques for sensor testing for computing devices during initial movement of the device, such as movement on a manufacturing line. In one instance, a device with integral sensor testing during initial movement of the device may include a plurality of sensors and a sensor test block coupled with the plurality of sensors, to detect, collect and/or report readings provided by at least some of the sensors in response to movement of the device between at least a first test station and a second test station. Other embodiments may be described and/or claimed.

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