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    Dynamically controlling power management of an on-die memory of a processor
    1.
    发明授权
    Dynamically controlling power management of an on-die memory of a processor 有权

    公开(公告)号：US09684360B2

    公开(公告)日：2017-06-20

    申请号：US14528076

    申请日：2014-10-30

    Applicant: Intel Corporation

    Inventor： Eli Kupermann ,  Elena Agranovsky

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.

    Technologies for automatic timing calibration in an inter-integrated circuit data bus
    2.
    发明授权
    Technologies for automatic timing calibration in an inter-integrated circuit data bus 有权

    公开(公告)号：US10229086B2

    公开(公告)日：2019-03-12

    申请号：US14998310

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Yuli Barcohen ,  Eli Kupermann ,  Alexander Brill

    IPC: G06F13/42 ,  G06F9/22

    Abstract: Technologies for controlling timing calibration of a dedicated inter-integrated circuit data bus by a primary microcontroller are disclosed. The primary microcontroller performs a data transfer with a secondary integrated circuit using the dedicated inter-integrated circuit data bus, and determines a duration of the data transfer. If the duration is outside of an acceptable range, the primary microcontroller updates one or more data transfer timing parameters so that the duration of future data transfers are closer to the acceptable range.

    Dynamically Controlling Power Management Of An On-Die Memory Of A Processor
    3.
    发明申请
    Dynamically Controlling Power Management Of An On-Die Memory Of A Processor 有权
    动态控制处理器的片上存储器的电源管理

    公开(公告)号：US20160124490A1

    公开(公告)日：2016-05-05

    申请号：US14528076

    申请日：2014-10-30

    Applicant: Intel Corporation

    Inventor： Eli Kupermann ,  Elena Agranovsky

    IPC: G06F1/32 ,  G06F12/02

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括：执行指令的至少一个核; 耦合到所述至少一个核的存储器，所述存储器包括用于存储信息的多个页面; 以及耦合到所述存储器的页面管理器，所述页面管理器访问与所述存储器的页面相关联的页表条目的元数据，并更新数据库的条目的使用信息，与所述存储器的页面相关联的数据库的条目 。 页面管理器可以至少部分地基于使用信息使至少一部分内存被动态地关机。 描述和要求保护其他实施例。

    TESTING OF DEVICE SENSORS ON A MANUFACTURING LINE
    5.
    发明申请
    TESTING OF DEVICE SENSORS ON A MANUFACTURING LINE 审中-公开

    公开(公告)号：US20170254683A1

    公开(公告)日：2017-09-07

    申请号：US15061535

    申请日：2016-03-04

    Applicant: Intel Corporation

    Inventor： Yael Yanai ,  Yehiel Shilo ,  Eli Kupermann ,  Chen-Hsun Wu ,  Elena Agranovsky ,  Marlon D. Bada

    IPC: G01D18/00

    Abstract: Embodiments of the present disclosure provide techniques for sensor testing for computing devices during initial movement of the device, such as movement on a manufacturing line. In one instance, a device with integral sensor testing during initial movement of the device may include a plurality of sensors and a sensor test block coupled with the plurality of sensors, to detect, collect and/or report readings provided by at least some of the sensors in response to movement of the device between at least a first test station and a second test station. Other embodiments may be described and/or claimed.

    Testing of device sensors on a manufacturing line
    6.
    发明授权
    Testing of device sensors on a manufacturing line 有权

    公开(公告)号：US10677618B2

    公开(公告)日：2020-06-09

    申请号：US15061535

    申请日：2016-03-04

    Applicant: Intel Corporation

    Inventor： Yael Yanai ,  Yehiel Shilo ,  Eli Kupermann ,  Chen-Hsun Wu ,  Elena Agranovsky ,  Marlon D. Bada

    IPC: G01D18/00

    Abstract: Embodiments of the present disclosure provide techniques for sensor testing for computing devices during initial movement of the device, such as movement on a manufacturing line. In one instance, a device with integral sensor testing during initial movement of the device may include a plurality of sensors and a sensor test block coupled with the plurality of sensors, to detect, collect and/or report readings provided by at least some of the sensors in response to movement of the device between at least a first test station and a second test station. Other embodiments may be described and/or claimed.

    Method and apparatus to manage power usage in a processor
    7.
    发明授权
    Method and apparatus to manage power usage in a processor 有权

    公开(公告)号：US09836113B2

    公开(公告)日：2017-12-05

    申请号：US14138564

    申请日：2013-12-23

    Applicant: Intel Corporation

    Inventor： Eli Kupermann ,  Rajasekaran Andiappan ,  Suryaprasad Kareenahalli ,  Yuli Barcohen

    IPC: G06F1/32

    CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In an embodiment, a processor includes first logic to determine first power to be provided to a first portion of a computational resource during a time period. The first portion may be reserved for execution by the processor of a first workload to be executed during the time period. The first power may be determined based at least in part on the first workload and independently of a second workload. The processor may include second logic to determine second power to be provided to a second portion of the computational resource during the time period. The second portion may be reserved for execution by the processor of the second workload during the time period. The second power may be determined based at least in part on the second workload and independently of the first workload.

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