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1.发明授权公开(公告)号：US09361064B2
公开(公告)日：2016-06-07
申请号：US14022683
申请日：2013-09-10
Applicant: INTEL CORPORATION
Inventor： Ofir Degani , Ashoke Ravi , Hasnain Lakdawala
CPC classification number: G06F5/00 , G04F10/005 , H03L7/085 , H03L2207/50 , H03M1/1014 , H03M1/1033
Abstract: Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop.
Abstract translation: 基于随机系统响应于线性相位斜坡生成的校准数据的统计分析，确定数字补偿以补偿配置为采样相位差的随机系统的非线性。 随机系统可以包括一组随机采样器电路，以在周期性事件中采样相位差，并且校准数据可以包括多个事件中的每一个的随机样本集合的数字值。 校准数据可以包括数字值的序列，其中数字值在随机系统的范围（即，随机系统的饱和状态之间）增加。 统计分析可以包括直方图分析来估计校准数据的概率分布。 随机系统可以被配置为时间 - 数字转换器的一部分，其可以配置在数字可控锁相环的反馈回路内。
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公开(公告)号：US09998162B2
公开(公告)日：2018-06-12
申请号：US15282622
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Eshel Gordon , Sophia Maerkovich , Ofir Degani , Hasnain Lakdawala
CPC classification number: H04B1/16 , H03M1/04 , H03M1/0656 , H03M1/0695 , H03M1/144 , H03M1/145 , H03M1/36 , H03M1/466
Abstract: Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.
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公开(公告)号：US20180097535A1
公开(公告)日：2018-04-05
申请号：US15282622
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Eshel Gordon , Sophia Maerkovich , Ofir Degani , Hasnain Lakdawala
CPC classification number: H04B1/16 , H03M1/04 , H03M1/0656 , H03M1/0695 , H03M1/144 , H03M1/145 , H03M1/36 , H03M1/466
Abstract: Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.
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