公开(公告)号：US20170207152A1

公开(公告)日：2017-07-20

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/76802 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2924/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US10049971B2

公开(公告)日：2018-08-14

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L21/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US09631065B2

公开(公告)日：2017-04-25

申请号：US13795021

申请日：2013-03-12

Applicant: INTEL CORPORATION

Inventor： Anna M. Prakash ,  James C. Matayabas ,  Arjun Krishnan ,  Nisha Ananthakrishnan

IPC: H01L21/56 ,  H01L23/29 ,  C08K5/00 ,  H01L21/78 ,  B23K26/18 ,  B23K26/364

CPC classification number: C08K5/005 ,  B23K26/18 ,  B23K26/364 ,  H01L21/563 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.